Subject: Re: [powerpc/nmi: RFC 2/2] Keep interrupts enabled even on soft disable

From: Benjamin Herrenschmidt <[email-masked]>
Date: Thu, 15 Dec 2016 09:15:29 -0600

On Wed, 2016-12-14 at 11:41 +1100, Balbir Singh wrote:
> I was planning to skipping other IRQ chips for now and support just
> XICS/XIVE with BOOK3S and PPC64. But we can discuss this.

Well you still need to make sure you don't do your lazy stuff on
them and actually mask EE.

> > That's why I mentioned opt-in. Maybe make it conditional on a
> > global
> > boolean that gets enabled by the PIC itself, or make it an enum
> > 
> > enum lazy_irq_masking_mode {
> >        lazy_irq_mask_ee,       /* Use CPU EE bit (default) */
> >        lazy_irq_mask_fetch,    /* Fetch the interrupt and stash it
> > away */
> >        lazy_irq_mask_prio      /* Change processor priority */
> > };
> > 
> > For the latter we'd need a ppc_md. hook to do the priority change
> > which xive (and potentially others like MPIC) could use.
> 
> We have set_cpu_priority for XICS, which sets the base_priority
> only for the CPPR at the moment. It can be extended

Well, that's what I said earlier. XICS can do that in *theory* but it's
broken in HW. There's a race condition or two, if you whack the CPPR in
a way that causes a pending interrupt to be rejected, there's a timing
window where the ICP can wedge itself or the interrupt be lost, I don't
remember.

The only safe way on XICS is to fetch the interrupt (which implicitly
raises the CPPR) and lower it using EOI.

Cheers,
Ben.