From: Benjamin Herrenschmidt <benh@kernel•crashing.org>
To: linuxppc-dev@ozlabs•org
Cc: "Aneesh Kumar K.V" <aneesh.kumar@linux•vnet.ibm.com>
Subject: [PATCH] powerpc/mm/radix: Update ERAT flushes when invalidating TLB
Date: Mon, 06 Feb 2017 13:05:16 +1100 [thread overview]
Message-ID: <1486346716.4850.82.camel@kernel.crashing.org> (raw)
Three tiny changes to the ERAT flushing logic: First don't make
it depend on DD1. It hasn't been decided yet but we might run
DD2 in a mode that also requires explicit flushes for performance
reasons so make it unconditional. We also add a missing isync, and
finally remove the flush from _tlbiel_va as it is only necessary
for congruence-class invalidations (PID, LPID and full TLB), not
targetted invalidations.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel•crashing.org>
---
arch/powerpc/mm/tlb-radix.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
index 61b7911..e0c8162 100644
--- a/arch/powerpc/mm/tlb-radix.c
+++ b/arch/powerpc/mm/tlb-radix.c
@@ -50,9 +50,7 @@ static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
for (set = 0; set < POWER9_TLB_SETS_RADIX ; set++) {
__tlbiel_pid(pid, set, ric);
}
- if (cpu_has_feature(CPU_FTR_POWER9_DD1))
- asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
- return;
+ asm volatile(PPC_INVALIDATE_ERAT ";isync" : : :"memory");
}
static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
@@ -85,8 +83,6 @@ static inline void _tlbiel_va(unsigned long va, unsigned long pid,
asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
asm volatile("ptesync": : :"memory");
- if (cpu_has_feature(CPU_FTR_POWER9_DD1))
- asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
}
static inline void _tlbie_va(unsigned long va, unsigned long pid,
next reply other threads:[~2017-02-06 2:05 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-06 2:05 Benjamin Herrenschmidt [this message]
2017-02-09 13:20 ` powerpc/mm/radix: Update ERAT flushes when invalidating TLB Michael Ellerman
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