[PATCH v9 6/8] powerpc: Swizzle around 4K PTE bits to free up bit 5 and bit 6

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From: Ram Pai <linuxram@us•ibm.com>
To: mpe@ellerman•id.au
Cc: linuxppc-dev@lists•ozlabs.org, benh@kernel•crashing.org,
	paulus@samba•org, khandual@linux•vnet.ibm.com,
	aneesh.kumar@linux•vnet.ibm.com, bsingharora@gmail•com,
	hbabu@us•ibm.com, mhocko@kernel•org, bauerman@linux•vnet.ibm.com,
	ebiederm@xmission•com, linuxram@us•ibm.com
Subject: [PATCH v9 6/8] powerpc: Swizzle around 4K PTE bits to free up bit 5 and bit 6
Date: Mon,  6 Nov 2017 00:50:50 -0800	[thread overview]
Message-ID: <1509958252-18302-7-git-send-email-linuxram@us.ibm.com> (raw)
In-Reply-To: <1509958252-18302-1-git-send-email-linuxram@us.ibm.com>

We need PTE bits 3 ,4, 5, 6 and 57 to support protection-keys,
because these are the bits we want to consolidate on across all
configuration to support protection keys.

Bit 3,4,5 and 6 are currently used on 4K-pte kernels. But bit 9
and 10 are available. Hence we use the two available bits and
free up bit 5 and 6. We will still not be able to free up bit 3
and 4. In the absence of any other free bits, we will have to
stay satisfied with what we have :-(. This means we will not
be able to support 32 protection keys, but only 8. The bit
numbers are big-endian as defined in the ISA3.0

This patch does the following change to 4K PTE.

H_PAGE_F_SECOND (S) which occupied bit 4 moves to bit 7.
H_PAGE_F_GIX (G,I,X) which occupied bit 5, 6 and 7 also moves
to bit 8,9, 10 respectively.
H_PAGE_HASHPTE (H) which occupied bit 8 moves to bit 4.

Before the patch, the 4k PTE format was as follows

 0 1 2 3 4  5  6  7  8 9 10....................57.....63
 : : : : :  :  :  :  : : :                      :     :
 v v v v v  v  v  v  v v v                      v     v
,-,-,-,-,--,--,--,--,-,-,-,-,-,------------------,-,-,-,
|x|x|x|B|S |G |I |X |H| | |x|x|................| |x|x|x|
'_'_'_'_'__'__'__'__'_'_'_'_'_'________________'_'_'_'_'

After the patch, the 4k PTE format is as follows

 0 1 2 3 4  5  6  7  8 9 10....................57.....63
 : : : : :  :  :  :  : : :                      :     :
 v v v v v  v  v  v  v v v                      v     v
,-,-,-,-,--,--,--,--,-,-,-,-,-,------------------,-,-,-,
|x|x|x|B|H |  |  |S |G|I|X|x|x|................| |.|.|.|
'_'_'_'_'__'__'__'__'_'_'_'_'_'________________'_'_'_'_'

The patch has no code changes; just swizzles around bits.

Signed-off-by: Ram Pai <linuxram@us•ibm.com>
---
 arch/powerpc/include/asm/book3s/64/hash-4k.h  |    7 ++++---
 arch/powerpc/include/asm/book3s/64/hash-64k.h |    1 +
 arch/powerpc/include/asm/book3s/64/hash.h     |    1 -
 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h b/arch/powerpc/include/asm/book3s/64/hash-4k.h
index ed0d1cd..8a91f24 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-4k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h
@@ -17,10 +17,11 @@
 #define H_PUD_TABLE_SIZE	(sizeof(pud_t) << H_PUD_INDEX_SIZE)
 #define H_PGD_TABLE_SIZE	(sizeof(pgd_t) << H_PGD_INDEX_SIZE)
 
-#define H_PAGE_F_GIX_SHIFT	56
-#define H_PAGE_F_SECOND	_RPAGE_RSV2	/* HPTE is in 2ndary HPTEG */
-#define H_PAGE_F_GIX	(_RPAGE_RSV3 | _RPAGE_RSV4 | _RPAGE_RPN44)
+#define H_PAGE_F_GIX_SHIFT	53
+#define H_PAGE_F_SECOND	_RPAGE_RPN44	/* HPTE is in 2ndary HPTEG */
+#define H_PAGE_F_GIX	(_RPAGE_RPN43 | _RPAGE_RPN42 | _RPAGE_RPN41)
 #define H_PAGE_BUSY	_RPAGE_RSV1     /* software: PTE & hash are busy */
+#define H_PAGE_HASHPTE	_RPAGE_RSV2     /* software: PTE & hash are busy */
 
 /* PTE flags to conserve for HPTE identification */
 #define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_HASHPTE | \
diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h
index b78d94e..62e101b 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-64k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h
@@ -14,6 +14,7 @@
 #define H_PAGE_COMBO	_RPAGE_RPN0 /* this is a combo 4k page */
 #define H_PAGE_4K_PFN	_RPAGE_RPN1 /* PFN is for a single 4k page */
 #define H_PAGE_BUSY	_RPAGE_RPN44     /* software: PTE & hash are busy */
+#define H_PAGE_HASHPTE	_RPAGE_RPN43	/* PTE has associated HPTE */
 
 /*
  * We need to differentiate between explicit huge page and THP huge
diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h
index e72474f..0920eff 100644
--- a/arch/powerpc/include/asm/book3s/64/hash.h
+++ b/arch/powerpc/include/asm/book3s/64/hash.h
@@ -9,7 +9,6 @@
  *
  */
 #define H_PTE_NONE_MASK		_PAGE_HPTEFLAGS
-#define H_PAGE_HASHPTE		_RPAGE_RPN43	/* PTE has associated HPTE */
 
 #ifdef CONFIG_PPC_64K_PAGES
 #include <asm/book3s/64/hash-64k.h>
-- 
1.7.1

next prev parent reply	other threads:[~2017-11-06  8:55 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-11-06  8:50 [PATCH v9 0/8] powerpc: Free up RPAGE_RSV bits Ram Pai
2017-11-06  8:50 ` [PATCH v9 1/8] powerpc: introduce pte_set_hidx() helper Ram Pai
2018-01-17 13:30   ` [v9,1/8] " Michael Ellerman
2017-11-06  8:50 ` [PATCH v9 2/8] powerpc: introduce pte_get_hash_gslot() helper Ram Pai
2017-11-06  8:50 ` [PATCH v9 3/8] powerpc: Free up four 64K PTE bits in 4K backed HPTE pages Ram Pai
2017-11-06  8:50 ` [PATCH v9 4/8] powerpc: Free up four 64K PTE bits in 64K " Ram Pai
2017-11-06  8:50 ` [PATCH v9 5/8] powerpc: shifted-by-one hidx value Ram Pai
2017-11-06  8:50 ` Ram Pai [this message]
2017-11-06  8:50 ` [PATCH v9 7/8] powerpc: use helper functions to get and set hash slots Ram Pai
2017-11-06  8:50 ` [PATCH v9 8/8] powerpc: capture the PTE format changes in the dump pte report Ram Pai

find likely ancestor, descendant, or conflicting patches for this message:
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dfblob:e72474f dfblob:0920eff )
 OR (
bs:"[PATCH v9 6/8] powerpc: Swizzle around 4K PTE bits to free up bit 5 and bit 6" )
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