Subject: R: Re: PCI device not working

From: Davide Viti <[email-masked]>
Date: Fri, 28 Sep 2012 16:48:54 +0200 (CEST)

Hi Kumar,

>
>It was, can you figure out in u-boot what exact config read on 
the bus would return the correct thing.
>
>The fact that when we probe the 
device at 0001:03 we should get back something like cfg_data=0xabba1b65

here 
follow some details about what is going on inside u-boot; verbosity increases 
from [1] to [3]

 [1] PCI printouts when the board come up
 [2] output of "pci 
[0-3] long" u-boot command
 [3] same as [1] but with debug print inside 
indirect_read_config_##size() [drivers/pci/pci_indirect.c]

if you were curious 
about our u-boot board settings, please refer to:
http://www.mail-archive.
com/[email-masked]/msg62007.html

thanx alot,
Davide

*************
*    [1]    *
*************
    PCIE1 used as Root Complex (base 
addr ffe09000)
               Scanning PCI bus 01
        01  00  1b65  abba  
0280  00
        cfg_addr:ffe09000  cfg_data:ffe09004  indirect_type:0
    
PCIE1 on bus 00 - 01

    PCIE2 used as Root Complex (base addr ffe0a000)

               Scanning PCI bus 03
        03  00  1b65  abba  0280  00
        
cfg_addr:ffe0a000  cfg_data:ffe0a004  indirect_type:0
    PCIE2 on bus 02 - 03

*************
*    [2]    *
*************

=> pci 0 long
Scanning PCI devices 
on bus 0

Found PCI device 00.00.00:
  vendor ID =                   0x1957
  
device ID =                   0x0100
  command register =            0x0006
  
status register =             0x0010
  revision ID =                 0x11
  
class code =                  0x0b (Processor)
  sub class code =              
0x20
  programming interface =       0x00
  cache line =                  0x08

  latency time =                0x00
  header type =                 0x01
  
BIST =                        0x00
  base address 0 =              0xfff00000
  
base address 1 =              0x00000000
  primary bus number =          0x00
  
secondary bus number =        0x01
  subordinate bus number =      0x01
  
secondary latency timer =     0x00
  IO base =                     0x00
  IO 
limit =                    0x00
  secondary status =            0x0000
  memory 
base =                 0xa000
  memory limit =                0xa000
  prefetch 
memory base =        0x1001
  prefetch memory limit =       0x0001
  prefetch 
memory base upper =  0x00000000
  prefetch memory limit upper = 0x00000000
  IO 
base upper 16 bits =       0x0000
  IO limit upper 16 bits =      0x0000
  
expansion ROM base address =  0x00000000
  interrupt line =              0x00
  
interrupt pin =               0x00
  bridge control =              0x0000

=> 
pci 1 long
Scanning PCI devices on bus 1

Found PCI device 01.00.00:kk
  vendor 
ID =                   0x1b65
  device ID =                   0xabba
  command 
register =            0x0006
  status register =             0x0010
  revision 
ID =                 0x01
  class code =                  0x02 (Network 
controller)
  sub class code =              0x80
  programming interface 
=       0x00
  cache line =                  0x08
  latency time 
=                0x00
  header type =                 0x00
  BIST 
=                        0x00
  base address 0 =              0xa0000000
  base 
address 1 =              0xa0010000
  base address 2 =              0x00000000

  base address 3 =              0x00000000
  base address 4 =              
0x00000000
  base address 5 =              0x00000000
  cardBus CIS pointer 
=         0x00000000
  sub system vendor ID =        0x0000
  sub system ID 
=               0x0000
  expansion ROM base address =  0x00000000
  interrupt 
line =              0x00
  interrupt pin =               0x01
  min Grant 
=                   0x00
  max Latency =                 0x00

=> pci 2 long

Scanning PCI devices on bus 2

Found PCI device 02.00.00:
  vendor ID 
=                   0x1957
  device ID =                   0x0100
  command 
register =            0x0006
  status register =             0x0010
  revision 
ID =                 0x11
  class code =                  0x0b (Processor)
  
sub class code =              0x20
  programming interface =       0x00
  cache 
line =                  0x08
  latency time =                0x00
  header type 
=                 0x01
  BIST =                        0x00
  base address 0 
=              0xfff00000
  base address 1 =              0x00000000
  primary 
bus number =          0x00
  secondary bus number =        0x01
  subordinate 
bus number =      0x01
  secondary latency timer =     0x00
  IO base 
=                     0x00
  IO limit =                    0x00
  secondary 
status =            0x0000
  memory base =                 0xb000
  memory 
limit =                0xb000
  prefetch memory base =        0x1001
  prefetch 
memory limit =       0x0001
  prefetch memory base upper =  0x00000000
  
prefetch memory limit upper = 0x00000000
  IO base upper 16 bits =       0x0000

  IO limit upper 16 bits =      0x0000
  expansion ROM base address =  
0x00000000
  interrupt line =              0x00
  interrupt pin =               
0x00
  bridge control =              0x0000

=> pci 3 long
Scanning PCI devices 
on bus 3

Found PCI device 03.00.00:
  vendor ID =                   0x1b65
  
device ID =                   0xabba
  command register =            0x0006
  
status register =             0x0010
  revision ID =                 0x01
  
class code =                  0x02 (Network controller)
  sub class code 
=              0x80
  programming interface =       0x00
  cache line 
=                  0x08
  latency time =                0x00
  header type 
=                 0x00
  BIST =                        0x00
  base address 0 
=              0xb0000000
  base address 1 =              0xb0010000
  base 
address 2 =              0x00000000
  base address 3 =              0x00000000

  base address 4 =              0x00000000
  base address 5 =              
0x00000000
  cardBus CIS pointer =         0x00000000
  sub system vendor ID 
=        0x0000
  sub system ID =               0x0000
  expansion ROM base 
address =  0x00000000
  interrupt line =              0x00
  interrupt pin 
=               0x01
  min Grant =                   0x00
  max Latency 
=                 0x00

*************
*    [3]    *
*************

    PCIE1 
used as Root Complex (base addr ffe09000)
b=0 d=0 f=0 (fbusno=0 itype=0 
cfg_adr=ffe09000 cfg_data=ffe09004) ofs=10 mask=0
...
               Scanning 
PCI bus 01
b=1 d=0 f=0 (fbusno=0 itype=0 cfg_adr=ffe09000 cfg_data=ffe09004) 
ofs=e mask=3
...
b=1 d=0 f=0 (fbusno=0 itype=0 cfg_adr=ffe09000 
cfg_data=ffe09004) ofs=3c mask=3
        01  00  1b65  abba  0280  00
b=1 d=1 
f=0 (fbusno=0 itype=0 cfg_adr=ffe09000 cfg_data=ffe09004) ofs=e mask=3
b=1 d=1 
f=0 (fbusno=0 itype=0 cfg_adr=ffe09000 cfg_data=ffe09004) ofs=0 mask=2
...
b=0 
d=0 f=0 (fbusno=0 itype=0 cfg_adr=ffe09000 cfg_data=ffe09004) ofs=9 mask=3
    
PCIE1 on bus 00 - 01

    PCIE2 used as Root Complex (base addr ffe0a000)
b=0 
d=0 f=0 (fbusno=2 itype=0 cfg_adr=ffe0a000 cfg_data=ffe0a004) ofs=10 mask=0
b=0 
d=0 f=0 (fbusno=2 itype=0 cfg_adr=ffe0a000 cfg_data=ffe0a004) ofs=10 mask=0
...

b=0 d=0 f=0 (fbusno=2 itype=0 cfg_adr=ffe0a000 cfg_data=ffe0a004) ofs=9 mask=3

               Scanning PCI bus 03
b=1 d=0 f=0 (fbusno=2 itype=0 
cfg_adr=ffe0a000 cfg_data=ffe0a004) ofs=e mask=3
b=1 d=0 f=0 (fbusno=2 itype=0 
cfg_adr=ffe0a000 cfg_data=ffe0a004) ofs=0 mask=2
...
b=1 d=0 f=0 (fbusno=2 
itype=0 cfg_adr=ffe0a000 cfg_data=ffe0a004) ofs=3c mask=3
        03  00  1b65  
abba  0280  00
        cfg_addr:ffe0a000  cfg_data:ffe0a004  indirect_type:0

b=1 d=1 f=0 (fbusno=2 itype=0 cfg_adr=ffe0a000 cfg_data=ffe0a004) ofs=e mask=3

...
b=0 d=0 f=0 (fbusno=2 itype=0 cfg_adr=ffe0a000 cfg_data=ffe0a004) ofs=9 
mask=3
    PCIE2 on bus 02 - 03

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