Subject: Re: [linux-fbdev] Re: readl() and friends and eieio on PPC

From: Richard Henderson <[email-masked]>
Date: Thu, 12 Aug 1999 00:33:18 -0700

On Thu, Aug 12, 1999 at 05:07:02PM +1000, Paul Mackerras wrote:
> > 10
> 
> One-cycle access to L1 cache, I guess?

No, 2 Cycles to L1 cache.  One cycle to execute the store,
which merely adds an entry to the store buffer.

> > 223
> 
> Because of i-cache misses, presumably

Presumably.  The 10 and 94 numbers are all that's interesting.

> Interesting.  Sounds like each wmb takes about 12 cycles ((94-10)/7),
> which sounds a bit like it is going all the way out to the memory bus
> and back before the cpu does the next instruction.
> 
> (Ob. nitpicking: if a wmb takes 12 cycles, how come we can do a wmb
> and 8 stores in 10 cycles? :-)

Because it doesn't work like that.  wmb adds a magic token to the
store buffer that prevents write combining and other such hw
optimizations.  Timing

	stq $31,addr
	stq $31,addr+8
vs
	stq $31,addr
	wmb
	stq $31,addr+8

shows only 1 cycle difference between the two.  I'm not quite sure
how the 12 works out.  I do know that L2 cache is 12 cycles away,
but that may just be coincidence.

Going all the way out to the memory bus would take a whole lot 
longer than 12 cycles.  More like 36.

> What numbers do you get on alpha if you point it at a framebuffer,
> just for interest?

I'll give that a try tomorrow.

r~

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