From: Marcelo Tosatti <marcelo.tosatti@cyclades•com>
To: Dan Malek <dan@embeddededge•com>
Cc: linux-ppc-embedded <linuxppc-embedded@ozlabs•org>
Subject: update DataTLBMiss exception comment
Date: Tue, 19 Apr 2005 08:52:53 -0300 [thread overview]
Message-ID: <20050419115253.GA2780@logos.cnet> (raw)
Hi,
Since v2.6 DataTLBMiss doesnt jump to the page fault handler, it instead
loads invalid TLB which in turn causes a DataTLBError exception.
The comment on top of it haven't been update since the change.
What about this?
--- head_8xx.S.orig 2005-04-19 13:29:14.000000000 -0300
+++ head_8xx.S 2005-04-19 13:34:44.000000000 -0300
@@ -289,13 +289,11 @@
* For the MPC8xx, this is a software tablewalk to load the instruction
* TLB. It is modelled after the example in the Motorola manual. The task
* switch loads the M_TWB register with the pointer to the first level table.
- * If we discover there is no second level table (the value is zero), the
- * plan was to load that into the TLB, which causes another fault into the
- * TLB Error interrupt where we can handle such problems. However, that did
- * not work, so if we discover there is no second level table, we restore
- * registers and branch to the error exception. We have to use the MD_xxx
- * registers for the tablewalk because the equivalent MI_xxx registers
- * only perform the attribute functions.
+ * If we discover there is no second level table (value is zero) or if there
+ * is an invalid pte, we load that into the TLB, which causes another fault
+ * into the TLB Error interrupt where we can handle such problems.
+ * We have to use the MD_xxx registers for the tablewalk because the
+ * equivalent MI_xxx registers only perform the attribute functions.
*/
InstructionTLBMiss:
#ifdef CONFIG_8xx_CPU6
next reply other threads:[~2005-04-19 16:42 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-04-19 11:52 Marcelo Tosatti [this message]
2005-04-19 16:57 ` update DataTLBMiss exception comment Dan Malek
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