Subject: Re: Not coherent cache DMA for G3/G4 CPUs: clarification needed

From: Eugene Surovegin <[email-masked]>
Date: Thu, 20 Apr 2006 14:02:01 -0700

On Thu, Apr 20, 2006 at 10:56:33PM +0200, Gerhard Pircher wrote:
> > --- Urspr?ngliche Nachricht ---
> > Von: Eugene Surovegin <[email-masked]>
> > An: Gerhard Pircher <[email-masked]>
> > Kopie: [email-masked], [email-masked]
> > Betreff: Re: Not coherent cache DMA for G3/G4 CPUs: clarification needed
> > Datum: Thu, 20 Apr 2006 13:38:48 -0700
> > 
> > There are already non-coherent cache PPC archs (8xx, 4xx) just look 
> > how all this implemented there, don't reinvent the wheel.
> > 
> > Also, read Documentation/DMA-API.txt and DMA-mapping.txt
> I know! Unfortunately this implementation does not work at all with G3/G4
> PPC desktop CPUs for various reasons (for example due to the BAT mapping,
> page tables with different access attributes for the same physical memory
> area allocated by the consistent DMA functions, etc.).

We have the same situation on 44x (all kernel memory is mapped 
through several big TLBs and consistent functions allocate additional 
cache-inhibited mappings for the same physical pages).

-- 
Eugene