Subject: Re: Not coherent cache DMA for G3/G4 CPUs: clarification needed

From: Brent Cook <[email-masked]>
Date: Fri, 21 Apr 2006 09:33:10 -0500

On Thursday 20 April 2006 23:38, Benjamin Herrenschmidt wrote:
> On Thu, 2006-04-20 at 14:55 -0700, Eugene Surovegin wrote:
> > On Thu, Apr 20, 2006 at 11:10:55PM +0200, Gerhard Pircher wrote:
> > > Well, Freescale's PPC programming environment manual clearly states
> > > that this will not work on G4 CPUs (74xx). Also Benjamin Herrenschmidt
> > > told me, that this implementation will not work for the reasons I
> > > mentioned before. The approach I'm trying to implement was his idea, so
> > > I have to trust in him.
> >
> > Well, you aren't the first person who tries to run G4 with
> > CONFIG_NOT_COHERENT_CACHE. This was done before and I don't remember
> > that those people had to implement anything as complex as you are
> > trying to do.
> >
> > You can try asking on #mklinux. It always better to ask people who
> > actually _did_ this :).
> >
> > In fact, I just grepped 2.6 and found
> > #ifdef(CONFIG_NOT_COHERENT_CACHE) in syslib/mv64x60.c. Guess what
> > systems usually have this type of bridge? Not 4xx/8xx, that's for sure.
>
> I think some folks tried ... and failed.
>
> Ben.

I'm not claiming to understand all of the issues here, but I have some 
MV64460 / MPC7448-based systems, and they only boot if 
CONFIG_NOT_COHERENT_CACHE=y

 - Brent