Subject: Re: [RFC/PATCH 14/16] MPIC MSI backend

From: David Miller <[email-masked]>
Date: Fri, 26 Jan 2007 19:02:16 -0800 (PST)

From: [email-masked] (Eric W. Biederman)
Date: Fri, 26 Jan 2007 19:46:22 -0700

> Paul Mackerras <[email-masked]> writes:
> 
> > Eric W. Biederman writes:
> >
> >> I believe the ppc model is to allocate an interrupt source on their
> >> existing interrupt controller and use that instead of the normal x86
> >> case of having the MSI interrupt go transparently to the cpu.
> >
> > Do you mean that x86 cpus themselves can actually be the target of a
> > write on the bus?  That's the first time I've heard of the CPU itself
> > being a target for a bus operation.
> 
> Yes.  The cpu front side bus is packet based on all modern x86 processors,
> and an irq message is one type of packet. 

Interesting.

This is exactly how all sparc64 chips have always worked too.  On
sparc64 the cpu can actually read in the packets and process them.
Can the x86 interrupt handler get at the full packet data?