Subject: Re: [RFC/PATCH 14/16] MPIC MSI backend

From: Grant Grundler <[email-masked]>
Date: Sat, 27 Jan 2007 11:30:28 -0700

On Sat, Jan 27, 2007 at 09:46:11AM +1100, Paul Mackerras wrote:
> Do you mean that x86 cpus themselves can actually be the target of a
> write on the bus?  That's the first time I've heard of the CPU itself
> being a target for a bus operation.

Though Eric gave a complete answer, I thought it was the Local-APIC
(onboard each CPU) is the target of the bus transaction. Intel
publishes the "Intel Interrupt Architecture" document and it describes
the API to the Local-APIC.  IA64 also uses an on-chip Local-APIC.

PA-RISC CPU (google for "PA-RISC External Interrupt Request Register")
is the target of _all_ IPI and IO interrupts (including MSI).
I think you'd find some of the comments in the PA-RISC interrupt
handling code interesting.
Look for txn_alloc_irq() in arch/parisc/kernel/irq.c.

My impression was any CPU that uses an IO-SAPIC (or -xAPIC) is
using bus transactions to communicate interrupts even if they
aren't using MSI. BIOS typically hides all the setup.

Alpha also uses bus transactions for IO interrupts. But I've read
through my ancient alpha reference manual and don't understand
exactly if the vector is part of the "DMA" transaction or is read
by the CPU off the I/O Bridge ("hose").

> Or do you mean there is some piece of hardware in the northbridge (or
> elsewhere) that accepts the MSI message writes and asserts an
> interrupt line to the CPU?  That is basically what we have on PPC.

*grin* PPC in this case looks more like "legacy x86" than x86 does today.
/me hides

hth,
grant