From: Valentine Barshak <vbarshak@ru•mvista.com>
To: linuxppc-dev@ozlabs•org
Subject: [ PATCH ] PowerPC cascade UIC IRQ handler fix.
Date: Mon, 30 Jul 2007 20:35:17 +0400 [thread overview]
Message-ID: <20070730163517.GA10087@ru.mvista.com> (raw)
PPC44x cascade UIC irq handler fix.
According to PPC44x UM, if an interrupt is configured as level-sensitive,
and a clear is attempted on the UIC_SR, the UIC_SR field is not
cleared if the incoming interrupt signal is at the asserted polarity.
This causes us to enter a cascade handler twice, since we first ack
parent UIC interrupt and ack child UIC one after that.
The patch checks child UIC msr value and returns IRQ_HANDLED
if there're no pending interrupts. Otherwise we get a kernel panic
with a "Fatal exception in interrupt" (illegal vector).
The patch also fixes status flags.
Signed-off-by: Valentine Barshak <vbarshak@ru•mvista.com>
---
--- linux.orig/arch/powerpc/sysdev/uic.c 2007-07-27 20:37:11.000000000 +0400
+++ linux/arch/powerpc/sysdev/uic.c 2007-07-30 20:26:48.000000000 +0400
@@ -142,7 +142,7 @@
desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
- if (trigger)
+ if (!trigger)
desc->status |= IRQ_LEVEL;
spin_unlock_irqrestore(&uic->lock, flags);
@@ -207,6 +207,9 @@
int subvirq;
msr = mfdcr(uic->dcrbase + UIC_MSR);
+ if (!msr)
+ return IRQ_HANDLED;
+
src = 32 - ffs(msr);
subvirq = irq_linear_revmap(uic->irqhost, src);
next reply other threads:[~2007-07-30 16:36 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-07-30 16:35 Valentine Barshak [this message]
2007-08-02 3:48 ` [ PATCH ] PowerPC cascade UIC IRQ handler fix David Gibson
2007-08-02 20:08 ` Josh Boyer
2007-08-03 11:09 ` Valentine Barshak
2007-08-03 1:18 ` Benjamin Herrenschmidt
2007-08-03 4:57 ` David Gibson
2007-08-03 6:23 ` David Gibson
2007-08-13 1:08 ` David Gibson
2007-08-13 12:31 ` Valentine Barshak
2007-08-14 1:35 ` David Gibson
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