Subject: [patch 1/2] powerpc: smp_wmb speedup

From: Nick Piggin <[email-masked]>
Date: Tue, 21 Aug 2007 04:16:52 +0200

This one is perhaps not as straightforward. I'm pretty limited in the types
of powerpc machines I can test with, so I don't actually know whether this
is the right thing to do on power5/6 etc. I can supply the simple test program
I used if anybody is interested.

---
On my dual G5, lwsync is over 5 times faster than eieio when used in a simple
test case (that actually makes real use of lwsync to provide write ordering).

This is not surprising, as it avoids the IO access synchronisation of eieio,
and still permits the important relaxation of executing loads before stores.
The on sub-architectures where lwsync is unavailable, eieio is retained, as
it should be faster than the alternative full sync (eieio is a proper subset
of sync).

Signed-off-by: Nick Piggin <[email-masked]>

Index: linux-2.6/include/asm-powerpc/system.h
===================================================================
--- linux-2.6.orig/include/asm-powerpc/system.h
+++ linux-2.6/include/asm-powerpc/system.h
@@ -43,7 +43,11 @@
 #ifdef CONFIG_SMP
 #define smp_mb()	mb()
 #define smp_rmb()	__asm__ __volatile__ (__stringify(LWSYNC) : : : "memory")
+#ifdef __SUBARCH_HAS_LWSYNC
+#define smp_wmb()	__asm__ __volatile__ (__stringify(LWSYNC) : : : "memory")
+#else
 #define smp_wmb()	eieio()
+#endif
 #define smp_read_barrier_depends()	read_barrier_depends()
 #else
 #define smp_mb()	barrier()