Subject: Device Tree updates for xilinx.

From: "Stephen Neuendorffer" <[email-masked]>
Date: Thu, 13 Dec 2007 15:41:16 -0800

These patches synchronize all the in-kernel drivers to use the
compatible names generated by the UBoot BSP generator.
(at git://git.xilinx.com/gen-mhs-devtree.git)

The patches to make this work are coming shortly:

patches 1-2 are provided for context only...  They're not ready for
mainline.  They provide 'raw' boot support and port some initialization
code from ARCH=3Dppc.
patches 3-7 are the interesting patches, which I think could be taken
for 2.6.25.

I've also pushed the working tree up to git.xilinx.com containing these
patches.  This tree also includes updates for ps2, gpio, etc.
The ll_temac currently doesn't work because I haven't gone back and
fixed the mechanism by which it finds out about the DMA that it is
connected to.

If you want output from the boot loader, you'll need something like:
		linux,stdout-path =3D "/plb_v34/opb_v20/serial@40400000";=20
This seems to work with uartlite, but I wasn't able to get it working
with a UART design.

Currently, you'll need to add, by hand the following labels:

mem_size_cells, on the toplevel #address-cells attribue, e,g. :
	mem_size_cells: #address-cells =3D <1>;

timebase, on the processors timebase-frequency attribute, e.g. :
			timebase: timebase-frequency =3D <11e1a300>;

memsize, on the memory's size, e.g.:
	DDR_256MB_32MX64_rank1_row13_col10_cl2_5: memory@0 {
		device_type =3D "memory";
		reg =3D < 0 memsize:10000000 >;
	} ;

In addition, if you're using uartlite, you'll have to specify
'console=3DttyUL0' as boot args.

For reference, below is the device tree for a Virtex2Pro design.  Except
for the changes noted above, this is entirely automatically generated.

Steve

/ {
	mem_size_cells: #address-cells =3D <1>;
	#size-cells =3D <1>;
	compatible =3D "xlnx,virtex";
	model =3D "testing";
	DDR_256MB_32MX64_rank1_row13_col10_cl2_5: memory@0 {
		device_type =3D "memory";
		reg =3D < 0 memsize:10000000 >;
	} ;
	chosen {
		bootargs =3D "root=3D/dev/nfs
nfsroot=3D172.19.221.221:/exports/xup/ydl41 ip=3Ddhcp console=3DttyUL0";
	} ;
	cpus {
		#address-cells =3D <1>;
		#cpus =3D <1>;
		#size-cells =3D <0>;
		PowerPC,405@0 {
			clock-frequency =3D <11e1a300>;
			d-cache-line-size =3D <20>;
			d-cache-size =3D <4000>;
			device_type =3D "cpu";
			i-cache-line-size =3D <20>;
			i-cache-size =3D <4000>;
			reg =3D <0>;
			timebase: timebase-frequency =3D <11e1a300>;
			xlnx,dcr-resync =3D <0>;
			xlnx,deterministic-mult =3D <0>;
			xlnx,disable-operand-forwarding =3D <1>;
			xlnx,mmu-enable =3D <1>;
		} ;
	} ;
	plb_v34 {
		#address-cells =3D <1>;
		#size-cells =3D <1>;
		compatible =3D "xlnx,plb-v34-1.02.a";
		ranges ;
		Ethernet_MAC: ethernet@80400000 {
			compatible =3D "xlnx,plb-ethernet-1.01.a";
			device_type =3D "network";
			interrupt-parent =3D <&opb_intc_0>;
			interrupts =3D < 2 0 >;
			local-mac-address =3D [ 00 00 00 00 00 00 ];
			reg =3D < 80400000 10000 >;
			xlnx,dev-blk-id =3D <0>;
			xlnx,dev-mir-enable =3D <1>;
			xlnx,dma-intr-coalesce =3D <1>;
			xlnx,dma-present =3D <1>;
			xlnx,err-count-exist =3D <1>;
			xlnx,fcs-insert-exist =3D <1>;
			xlnx,half-duplex-exist =3D <1>;
			xlnx,include-dev-pencoder =3D <1>;
			xlnx,ipif-fifo-depth =3D <8000>;
			xlnx,mac-fifo-depth =3D <40>;
			xlnx,mii-exist =3D <1>;
			xlnx,miim-clkdvd =3D <13>;
			xlnx,pad-insert-exist =3D <1>;
			xlnx,reset-present =3D <1>;
			xlnx,source-addr-insert-exist =3D <1>;
		} ;
		opb_v20 {
			#address-cells =3D <1>;
			#size-cells =3D <1>;
			compatible =3D "xlnx,opb-v20-1.10.c";
			ranges ;
			Audio_Codec: opb-ac97@7d400000 {
				compatible =3D "xlnx,opb-ac97-2.00.a";
				interrupt-parent =3D <&opb_intc_0>;
				interrupts =3D < 1 0 >;
				reg =3D < 7d400000 10000 >;
				xlnx,intr-level =3D <1>;
				xlnx,playback =3D <1>;
				xlnx,record =3D <1>;
				xlnx,use-bram =3D <1>;
			} ;
			DIPSWs_4Bit: opb-gpio@40020000 {
				compatible =3D "xlnx,opb-gpio-3.01.b";
				reg =3D < 40020000 10000 >;
				xlnx,all-inputs =3D <1>;
				xlnx,all-inputs-2 =3D <0>;
				xlnx,dout-default =3D <0>;
				xlnx,dout-default-2 =3D <0>;
				xlnx,gpio-width =3D <4>;
				xlnx,interrupt-present =3D <0>;
				xlnx,is-bidir =3D <1>;
				xlnx,is-bidir-2 =3D <1>;
				xlnx,is-dual =3D <0>;
				xlnx,tri-default =3D <ffffffff>;
				xlnx,tri-default-2 =3D <ffffffff>;
				xlnx,user-id-code =3D <3>;
			} ;
			LEDs_4Bit: opb-gpio@40000000 {
				compatible =3D "xlnx,opb-gpio-3.01.b";
				reg =3D < 40000000 10000 >;
				xlnx,all-inputs =3D <0>;
				xlnx,all-inputs-2 =3D <0>;
				xlnx,dout-default =3D <0>;
				xlnx,dout-default-2 =3D <0>;
				xlnx,gpio-width =3D <4>;
				xlnx,interrupt-present =3D <0>;
				xlnx,is-bidir =3D <0>;
				xlnx,is-bidir-2 =3D <1>;
				xlnx,is-dual =3D <0>;
				xlnx,tri-default =3D <ffffffff>;
				xlnx,tri-default-2 =3D <ffffffff>;
				xlnx,user-id-code =3D <3>;
			} ;
			PS2_Ports: opb-ps2-dual-ref@7a400000 {
				#address-cells =3D <1>;
				#size-cells =3D <1>;
				compatible =3D "xlnx,compound";
				ranges =3D < 0 7a400000 10000 >;
				opb-ps2-dual-ref@0 {
					compatible =3D
"xlnx,opb-ps2-dual-ref-1.00.a";
					interrupt-parent =3D
<&opb_intc_0>;
					interrupts =3D < 6 0 >;
					reg =3D < 0 40 >;
				} ;
				opb-ps2-dual-ref@1000 {
					compatible =3D
"xlnx,opb-ps2-dual-ref-1.00.a";
					interrupt-parent =3D
<&opb_intc_0>;
					interrupts =3D < 5 0 >;
					reg =3D < 1000 40 >;
				} ;
			} ;
			PushButtons_5Bit: opb-gpio@40040000 {
				compatible =3D "xlnx,opb-gpio-3.01.b";
				reg =3D < 40040000 10000 >;
				xlnx,all-inputs =3D <1>;
				xlnx,all-inputs-2 =3D <0>;
				xlnx,dout-default =3D <0>;
				xlnx,dout-default-2 =3D <0>;
				xlnx,gpio-width =3D <5>;
				xlnx,interrupt-present =3D <0>;
				xlnx,is-bidir =3D <1>;
				xlnx,is-bidir-2 =3D <1>;
				xlnx,is-dual =3D <0>;
				xlnx,tri-default =3D <ffffffff>;
				xlnx,tri-default-2 =3D <ffffffff>;
				xlnx,user-id-code =3D <3>;
			} ;
			RS232_Uart_1: serial@40400000 {
				compatible =3D "xlnx,opb-uartlite-1.00.b";
				device_type =3D "serial";
				interrupt-parent =3D <&opb_intc_0>;
				interrupts =3D < 4 0 >;
				port-number =3D <0>;
				reg =3D < 40400000 10000 >;
				xlnx,baudrate =3D <2580>;
				xlnx,clk-freq =3D <5f5e100>;
				xlnx,data-bits =3D <8>;
				xlnx,odd-parity =3D <0>;
				xlnx,use-parity =3D <0>;
			} ;
			SysACE_CompactFlash: opb-sysace@41800000 {
				compatible =3D "xlnx,opb-sysace-1.00.c";
				interrupt-parent =3D <&opb_intc_0>;
				interrupts =3D < 3 0 >;
				reg =3D < 41800000 10000 >;
				xlnx,mem-width =3D <10>;
			} ;
			dcr_v29 {
				#address-cells =3D <1>;
				#size-cells =3D <1>;
				compatible =3D "xlnx,dcr-v29-1.00.a";
				ranges =3D < 0 40700000 1000 >;
				VGA_FrameBuffer: plb-tft-cntlr-ref@200 {
					compatible =3D
"xlnx,plb-tft-cntlr-ref-1.00.a";
					reg =3D < 200 8 >;
					xlnx,default-tft-base-addr =3D
<7f>;
					xlnx,dps-init =3D <1>;
					xlnx,on-init =3D <1>;
					xlnx,pixclk-is-busclk-divby4 =3D
<1>;
				} ;
			} ;
			onewire_0: opb-onewire@7a200000 {
				compatible =3D "xlnx,opb-onewire-1.00.a";
				reg =3D < 7a200000 10000 >;
				xlnx,add-pullup =3D "true";
				xlnx,checkcrc =3D "true";
				xlnx,clk-div =3D <f>;
			} ;
			opb_hwicap_0: opb-hwicap@41300000 {
				compatible =3D "xlnx,opb-hwicap-1.00.b";
				reg =3D < 41300000 10000 >;
			} ;
			opb_intc_0: interrupt-controller@41200000 {
				#interrupt-cells =3D <2>;
				compatible =3D "xlnx,opb-intc-1.00.c";
				interrupt-controller ;
				reg =3D < 41200000 10000 >;
				xlnx,num-intr-inputs =3D <7>;
			} ;
			opb_timer_0: opb-timer@40800000 {
				compatible =3D "xlnx,opb-timer-1.00.b";
				interrupt-parent =3D <&opb_intc_0>;
				interrupts =3D < 0 0 >;
				reg =3D < 40800000 100 >;
				xlnx,count-width =3D <20>;
				xlnx,gen0-assert =3D <1>;
				xlnx,gen1-assert =3D <1>;
				xlnx,one-timer-only =3D <0>;
				xlnx,trig0-assert =3D <1>;
				xlnx,trig1-assert =3D <1>;
			} ;
		} ;
	} ;
}  ;