Subject: Re: ARCH=ppc -> ARCH=powerpc : help needed for dts file

From: Philippe De Muyter <[email-masked]>
Date: Tue, 4 Mar 2008 10:10:59 +0100

Hi Ben,

On Tue, Mar 04, 2008 at 07:22:19PM +1100, Benjamin Herrenschmidt wrote:
> 
> On Tue, 2008-03-04 at 09:08 +0100, Philippe De Muyter wrote:
> > With ARCH=ppc, all those interrupt's info's are hardcoded in the .c
> > files.
> > But I expected I could fill the dts file for ARCH=powerpc from info's
> > I
> > could collect in /proc on a running ARCH=ppc linux without dts file
> > for the same board.
> 
> Rather, look at the C file. Send it and we can help figuring things out.

Thanks in advance

Philippe

I also attach my current (not working) dts file attempt.  It is actually
a modified mpc8540ads.dts file.

I now thinks that the ide-cs (hda) discovery or not depends on the cold
or warm reboot.

Here are the patches for my config (MEIP_8540) relative to a vanilla
linux-2.6.24.  I hacked the MPC8540ADS config. The PCI4520 is the
multi-function chip from TI (dual-socket pc-card + iee1394 ohci and two-port
phy)

--- ./arch/ppc/platforms/85xx/mpc85xx_ads_common.cbk	2008-01-24 22:58:37.000000000 +0000
+++ ./arch/ppc/platforms/85xx/mpc85xx_ads_common.c	2008-02-20 16:54:33.000000000 +0000
@@ -58,6 +58,29 @@
 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
 static u_char mpc85xx_ads_openpic_initsenses[] __initdata = {
 	MPC85XX_INTERNAL_IRQ_SENSES,
+#ifdef CONFIG_MEIP_8540
+	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	// External 0 : nINTPFO
+	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	// External 1 : nINTRTC
+	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	// External 2 : nINTPLD
+	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	// External 3 : nINTSTX
+	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	// External 4 : nINTPHY
+#if defined(CONFIG_PCI)
+	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 5 : PCI4520 MFUNC 0 */
+	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 6 : PCI4520 MFUNC 1 */
+	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 7 : PCI4520 MFUNC 2 */
+	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 8 : PCI4520 MFUNC 3 */
+	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 9 : PCI4520 MFUNC 4 */
+	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 10 : PCI4520 MFUNC 5 */
+	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 11 : PCI4520 MFUNC 6 */
+#else
+	0x0,						/* External  6: */
+	0x0,						/* External  7: */
+	0x0,						/* External  8: */
+	0x0,						/* External  9: */
+	0x0,						/* External 10: */
+	0x0,						/* External 11: */
+#endif
+#else
 	0x0,						/* External  0: */
 #if defined(CONFIG_PCI)
 	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* External 1: PCI slot 0 */
@@ -77,6 +100,7 @@
 	0x0,				/* External  9: */
 	0x0,				/* External 10: */
 	0x0,				/* External 11: */
+#endif
 };
 
 /* ************************************************************************ */
--- ./arch/ppc/platforms/85xx/mpc85xx_ads_common.hbk	2008-01-24 22:58:37.000000000 +0000
+++ ./arch/ppc/platforms/85xx/mpc85xx_ads_common.h	2008-02-20 16:36:07.000000000 +0000
@@ -29,10 +29,17 @@
 extern void mpc85xx_ads_map_io(void) __init;
 
 /* PCI interrupt controller */
+#ifdef CONFIG_MEIP_8540
+#define PIRQA		MPC85xx_IRQ_EXT5
+#define PIRQB		MPC85xx_IRQ_EXT6
+#define PIRQC		MPC85xx_IRQ_EXT7
+#define PIRQD		MPC85xx_IRQ_EXT8
+#else
 #define PIRQA		MPC85xx_IRQ_EXT1
 #define PIRQB		MPC85xx_IRQ_EXT2
 #define PIRQC		MPC85xx_IRQ_EXT3
 #define PIRQD		MPC85xx_IRQ_EXT4
+#endif
 
 #define MPC85XX_PCI1_LOWER_IO	0x00000000
 #define MPC85XX_PCI1_UPPER_IO	0x00ffffff