Subject: Re: [PATCH] 4xx: Workaround for CHIP_11 Errata

From: Stefan Roese <[email-masked]>
Date: Thu, 15 May 2008 17:16:43 +0200

On Thursday 15 May 2008, Josh Boyer wrote:
> The PowerPC 440EP, 440GR, 440EPx, and 440GRx chips have an issue that
> causes the PLB3-to-PLB4 bridge to wait indefinitely for transaction
> requests that cross the end-of-memory-range boundary.  Since the DDR
> controller only returns the valid portion of a read request, the bridge
> will prevent other PLB masters from completing their transactions.
>
> This implements the recommended workaround for this errata for chips that
> use older versions of firmware that do not already handle it.  The last
> 4KiB of memory are hidden from the kernel to prevent the problem
> transactions from occurring.
>
> Signed-off-by: Josh Boyer <[email-masked]>

Acked-by: Stefan Roese <[email-masked]>

Thanks.

Best regards,
Stefan