Subject: Re: [PATCH] [POWERPC] 85xx: Add next-level-cache property

From: Nathan Lynch <[email-masked]>
Date: Mon, 2 Jun 2008 16:26:32 -0500

Segher Boessenkool wrote:
>>>
>>> The PowerPC binding defines an "l2-cache" property for this (it
>>> points from CPU node to L2 cache node, from L2 cache node to L3
>>> cache node, from L3 cache node to L4 cache node, etc.)
>>
>> So looking at the PPC binding its not terrible clear about "l3-cache"  
>> being a valid property.
>
> It isn't.  The property is called "l2-cache" at every level.
>
>> I believe the discussion w/ePAPR was to create something a bit more  
>> generic and clarify/update the PPC binding.
>
> Nasty.  Sure, "l2-cache" isn't the nicest name to point to deeper
> cache levels, but introducing a new property with (substantially)
> the same semantics is worse.

The semantics appear to be identical, even.

> There really shouldn't be a new property name until new functionality
> is introduced.  For example, it could allow to describe more than one
> cache at each level (the current binding already allows more than one
> parent for each cache, but only one child; and cache hierarchies like
> that actually exist).
>
>> I'm going to stick with the new binding as we don't use this linking  
>> currently.
>
> Dunno what's the best thing to do here.  If you don't need the
> functionality yet, it might be best to postpone putting either
> property in there.  Sigh, what a mess.

Does existing practice count for anything?  IBM pseries firmware uses
the l2-cache property as described in the PowerPC binding.