From: Grant Likely <grant.likely@secretlab•ca>
To: Andre Schwarz <andre.schwarz@matrix-vision•de>
Cc: linux-ppc list <linuxppc-dev@ozlabs•org>
Subject: Re: [PATCH] MPC52xx PCI write combine timer
Date: Thu, 10 Jul 2008 08:58:07 -0600 [thread overview]
Message-ID: <20080710145807.GB446@secretlab.ca> (raw)
In-Reply-To: <4875DC0C.2060609@matrix-vision.de>
On Thu, Jul 10, 2008 at 11:53:16AM +0200, Andre Schwarz wrote:
> On MPC52xx the PCI target control register (PCITCR) @ MBAR + 0xD6C is initialized with
> only bit 7 (Latrule disable) set. The 8-Bit write combine timer (Bits 24..31) should be
> also set to a reasonable value _greater zero_ (0x08 = default) since setting it to 0x00
> leads to _very poor_ performance as a PCI target since external burst won't be possible
> at all.
>
> Setting the WCT to 0x08 (cache-line size) leads to good overall perfomance.
Looks good to me. I'll test it here and pick it up if all looks good.
Cheers,
g.
prev parent reply other threads:[~2008-07-10 14:58 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-07-10 9:53 [PATCH] MPC52xx PCI write combine timer Andre Schwarz
2008-07-10 14:58 ` Grant Likely [this message]
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