Subject: Re: [PATCH] powerpc: i2c-mpc: make speed registers configurable via FDT

From: Grant Likely <[email-masked]>
Date: Thu, 31 Jul 2008 14:48:38 -0600

On Thu, Jul 31, 2008 at 03:37:07PM -0500, Timur Tabi wrote:
> Grant Likely wrote:
> 
> > How is the divider controlled?  Is it a fixed property of the SoC? 
> 
> Yes.  The divider is either 1, 2, or 3, and the only way to know which one
> it is is to look up the specific SOC model number.  And depending on the
> SOC model, there may also be a register that needs to be looked up.
> 
> > a
> > shared register setting? or a register setting within the i2c device?
> 
> The I2C device itself has no idea what the divider is.  It only sees the
> result of the divider.

Then that absolutely suggests to me that either the final clock or the
divider should be encoded in the i2c node; not in the soc node.

g.