Subject: Re: GPIO - marking individual pins (not) available in device tree

From: Anton Vorontsov <[email-masked]>
Date: Mon, 27 Oct 2008 21:34:21 +0300

On Mon, Oct 27, 2008 at 10:40:12AM -0500, Matt Sealey wrote:
>
>
> David Gibson wrote:
>
>> Um.. I can't actually follow what you're getting at there, sorry.
>
> Imagine in your head that you have a GPIO controller that has a
> 32-bit register potentially controlling 32 pins on the chip.
>
> Imagine that rather than being able to allocate 6 GPIO pins
> *right next to each other* in the register and saying that
> you start at "pin" 15 and use the next 6 "pins", you have to
> spread it around and use pin 1, pin 8, pin 9, pin 11, pin 15,
> pin 30, to make up this peripheral.

Isn't this some implementation detail of a gpio controller?

gpio: gpio-controller@... {
	#gpio-cells = <2>;
	compatible = "gpio-bank-with-funny-mapping"; <- notice this
	reg = <123 4>;
	gpio-controller;
}

device {
	gpios = <&gpio 0 0 &gpio 1 0 &gpio 2 0>;
}

^^ Three gpios, 0, 1, 2. Based on a compatible entry Linux can
   translate them in any way.

   For example GPIO0 - bit 15, GPIO1 - bit 20, GPIO2 - bit 1.

> As far as I can tell there is no way at all to specify a set of
> GPIO pins which are NOT consecutive because the current GPIO
> spec stops after specifying a controller bank (the 32-bit
> register).

The GPIO spec doesn't specify a controller bank. It says

- - - -
gpio-specifier may encode: bank, pin position inside the bank,
whether pin is open-drain and whether pin is logically inverted.
- - - -

May encode. Or may not encode. FYI, for most (all) SOC GPIO
controllers we don't use "bank" encoding in the gpio-specifier.

-- 
Anton Vorontsov
email: [email-masked]
irc://irc.freenode.net/bd2