From: "Gerhard Pircher" <gerhard_pircher@gmx•net>
To: "Roderick Colenbrander" <thunderbird2k@gmx•net>, linuxppc-dev@ozlabs•org
Subject: Re: DTS file PCI / i8259 for Xilinx ML510
Date: Sun, 15 Mar 2009 11:43:13 +0100 [thread overview]
Message-ID: <20090315104313.72510@gmx.net> (raw)
In-Reply-To: <20090315083826.302680@gmx.net>
-------- Original-Nachricht --------
> Datum: Sun, 15 Mar 2009 09:38:26 +0100
> Von: "Roderick Colenbrander" <thunderbird2k@gmx•net>
> An: "Gerhard Pircher" <gerhard_pircher@gmx•net>, linuxppc-dev@ozlabs•org
> Betreff: Re: DTS file PCI / i8259 for Xilinx ML510
> > > At some point in the file they create some (dummy?) pcie section in
> > > which they define a uli1575, an isa bus and attached to that isa bus
> > > a i8259. Is this the correct way of doing things? The i8259 driver
> > > seems to use io ports 0x20-21/0xa0-0xa1/0x4d0-0x4d1 those are also
> > > defined below but how are those mapped to the south bridge? I have
> > > seen some code in kernel/isa-bridge, is that code indeed responsible
> > > for setting up these ports?
> > Yes, the pcie node is the PCI host bridge node and the uli1571 node
> > acts as PCI2ISA bridge node. AFAIK their ranges properties are parsed
> > by pci_process_bridge_OF_ranges().
> > IIRC the code in kernel/isa-bridge is used for 64bit PPC machines only
> > for now. The I/O addresses for the i8259 PIC are currently hardcoded
> > and setup (request_resource()) in sysdev/i8259.c.
>
> I got the i8259 south bridge working now after adding an io_base_virt
> offset to all inb/outb lines in sysdev/i8259.c. Would it be worth all
> the troubles to add ppc32 support to isa-bridge.c? The whole point of
> the code is basically to remap the io memory to low addresses for these
> 64-bit ppc systems (mainly freescale boards with a i8259 and pseries
> systems with a i8259).
pci_process_bridge_OF_ranges() should "ioremap" io_base_virt for you,
if your board has only one PCI I/O space. It also sets isa_io_base to
io_base_virt on PPC32, but expects that the ISA I/O space is mapped to
PCI I/O address 0x0. Isn't that the case for your board?
> As far as I have seen it is only needed for i8259 interrupt controllers.
> Personally I think it would be better to pass a io base offset to
> i8259_setup or so. Or perhaps do some dts file parsing in i8259.c.
> I'm not sure what the proper layout would be for this in the dts file
> though.
I think adding an io base offset parameter to i8259_setup isn't the
right way to do it. I would expect other problems too, if ISA I/O space
isn't mapped 1:1 to PCI I/O space on a PPC32 system. Maybe a more
experienced kernel developer can comment on this?
> With those changes I mentioned to i8259.c I got some PCI devices of my
> ali m1553 south bridge working. The code is ugly and I need to do
> cleanups. When it is done I will submit some patches.
IMHO that doesn't matter, as long as it helps people to understand your
problem. :-)
regards,
Gerhard
--
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next prev parent reply other threads:[~2009-03-15 10:43 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-03-12 10:32 DTS file PCI / i8259 for Xilinx ML510 Roderick Colenbrander
2009-03-14 21:54 ` Gerhard Pircher
2009-03-15 8:38 ` Roderick Colenbrander
2009-03-15 10:43 ` Gerhard Pircher [this message]
2009-03-15 11:00 ` Roderick Colenbrander
2009-03-15 13:40 ` Gerhard Pircher
2009-03-16 8:18 ` Roderick Colenbrander
2009-03-16 9:42 ` Roderick Colenbrander
-- strict thread matches above, loose matches on Subject: below --
2009-03-12 10:43 Roderick Colenbrander
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