From: Scott Wood <scottwood@freescale•com>
To: Joakim Tjernlund <joakim.tjernlund@transmode•se>
Cc: Rex Feany <RFeany@mrv•com>,
"linuxppc-dev@ozlabs•org" <linuxppc-dev@ozlabs•org>
Subject: Re: [PATCH 0/8] Fix 8xx MMU/TLB
Date: Fri, 30 Oct 2009 12:16:07 -0500 [thread overview]
Message-ID: <20091030171607.GA781@loki.buserror.net> (raw)
In-Reply-To: <OFA43B9FDF.F43B1705-ONC1257652.0041B12F-C1257652.004211A3@transmode.se>
On Sat, Oct 17, 2009 at 02:01:38PM +0200, Joakim Tjernlund wrote:
> + mfspr r10, SPRN_SRR0
> DO_8xx_CPU6(0x3780, r3)
> mtspr SPRN_MD_EPN, r10
> mfspr r11, SPRN_M_TWB /* Get level 1 table entry address */
> - lwz r11, 0(r11) /* Get the level 1 entry */
> + cmplwi cr0, r11, 0x0800
> + blt- 3f /* Branch if user space */
> + lis r11, swapper_pg_dir@h
> + ori r11, r11, swapper_pg_dir@l
> + rlwimi r11, r11, 0, 2, 19
That rlwimi is a no-op -- I think you meant to use a different register
here?
> +3: lwz r11, 0(r11) /* Get the level 1 entry */
> DO_8xx_CPU6(0x3b80, r3)
> mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
> mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
> lwz r11, 0(r11) /* Get the pte */
> /* concat physical page address(r11) and page offset(r10) */
> rlwimi r11, r10, 0, 20, 31
But r10 here contains SRR0 from above, and this is a data TLB error.
-Scott
next prev parent reply other threads:[~2009-10-30 17:16 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-10-15 9:04 [PATCH 0/8] Fix 8xx MMU/TLB Joakim Tjernlund
2009-10-15 9:04 ` [PATCH 1/8] 8xx: invalidate non present TLBs Joakim Tjernlund
2009-10-15 9:04 ` [PATCH 2/8] 8xx: Update TLB asm so it behaves as linux mm expects Joakim Tjernlund
2009-10-15 9:04 ` [PATCH 3/8] 8xx: Tag DAR with 0x00f0 to catch buggy instructions Joakim Tjernlund
2009-10-15 9:04 ` [PATCH 4/8] 8xx: Fixup DAR from buggy dcbX instructions Joakim Tjernlund
2009-10-15 9:04 ` [PATCH 5/8] 8xx: Add missing Guarded setting in DTLB Error Joakim Tjernlund
2009-10-15 9:04 ` [PATCH 6/8] 8xx: Restore _PAGE_WRITETHRU Joakim Tjernlund
2009-10-15 9:04 ` [PATCH 7/8] 8xx: start using dcbX instructions in various copy routines Joakim Tjernlund
2009-10-15 9:04 ` [PATCH 8/8] 8xx: Remove DIRTY pte handling in DTLB Error Joakim Tjernlund
2009-10-15 16:56 ` [PATCH 0/8] Fix 8xx MMU/TLB Rex Feany
2009-10-16 8:16 ` Joakim Tjernlund
2009-10-16 20:25 ` Rex Feany
2009-10-17 11:24 ` Joakim Tjernlund
[not found] ` <OF2BB5EF59.1EE0A77D-ONC1257652.003D79DC-C1257652.003EA687@LocalDomain>
2009-10-17 12:01 ` Joakim Tjernlund
2009-10-26 22:47 ` Benjamin Herrenschmidt
2009-10-26 23:26 ` Dan Malek
2009-10-27 0:00 ` Benjamin Herrenschmidt
2009-10-27 9:16 ` Joakim Tjernlund
2009-10-27 15:58 ` Scott Wood
2009-10-27 16:38 ` Joakim Tjernlund
2009-10-30 0:12 ` Scott Wood
2009-10-30 0:51 ` Joakim Tjernlund
2009-10-30 17:16 ` Scott Wood [this message]
2009-10-30 17:37 ` Scott Wood
2009-10-31 10:31 ` Joakim Tjernlund
2009-11-03 13:32 ` Joakim Tjernlund
2009-11-03 16:59 ` Scott Wood
2009-11-03 17:16 ` Joakim Tjernlund
2009-10-15 22:04 ` Scott Wood
-- strict thread matches above, loose matches on Subject: below --
2009-10-11 16:35 Joakim Tjernlund
2009-10-14 17:23 ` Scott Wood
2009-10-14 18:46 ` Joakim Tjernlund
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