Subject: Re: MPC831x (and others?) NAND erase performance improvements

From: Mark Mason <[email-masked]>
Date: Tue, 7 Dec 2010 13:23:17 -0500

David Laight <[email-masked]> wrote:

> > The problem cropped up when there was a lot of traffic to the NAND
> > (Samsung K9WAGU08U1B-PIB0), with the NAND being on the LBC along with
> > a video chip that needed constant and prompt attention.
> > 
> > What I would see is that, as the writes happened, the erases would
> > wind up batched and issued all at once, such that frequently 400-700
> > erases were issued in rapid succession with a 1ms LBC BUSY cycle per
> > erase.
> 
> Are those just the reads of the status register polling to
> determine when the sector erase has completed ?

No, it's not, since it isn't polling the status register.  It's using
a hardware line from the NAND to indicate that the NAND is busy.  That
one hardware line is shared between all devices on the bus, so if one
device says it's busy then all bus traffic stops until the NAND
deasserts the busy line.