From: Michael Ellerman <michael@ellerman•id.au>
To: Sukadev Bhattiprolu <sukadev@linux•vnet.ibm.com>
Cc: linuxppc-dev@ozlabs•org, Paul Mackerras <paulus@samba•org>,
Anshuman Khandual <khandual@linux•vnet.ibm.com>
Subject: Re: [PATCH 2/8] powerpc/perf: Rework disable logic in pmu_disable()
Date: Wed, 10 Jul 2013 12:12:15 +1000 [thread overview]
Message-ID: <20130710021214.GB7491@concordia> (raw)
In-Reply-To: <20130710001523.GA24980@us.ibm.com>
On Tue, Jul 09, 2013 at 05:15:23PM -0700, Sukadev Bhattiprolu wrote:
> Anshuman Khandual [khandual@linux•vnet.ibm.com] wrote:
> | On 06/24/2013 04:58 PM, Michael Ellerman wrote:
> | > In pmu_disable() we disable the PMU by setting the FC (Freeze Counters)
> | > bit in MMCR0. In order to do this we have to read/modify/write MMCR0.
> | >
> | > It's possible that we read a value from MMCR0 which has PMAO (PMU Alert
> | > Occurred) set. When we write that value back it will cause an interrupt
> | > to occur. We will then end up in the PMU interrupt handler even though
> | > we are supposed to have just disabled the PMU.
> | >
> |
> | Is that possible ? First of all MMCR0[PMAO] could not be written by SW.
> | Even if you try writing it, how its going to generate PMU interrupt ?
> | HW sets this bit MMCR0[PMAO] after a PMU interrupt has already occurred
> | not that if we set this, a PMU interrupt would be generated.
>
> Looks like writing 1 MMCR0[PMAO] is allowed (to save interrupts across
> partition swaps) and it does generate the interrupt.
Yes it's documented in the ISA.
> | > We can avoid this by making sure we never write PMAO back. We should not
> |
> | Making sure that we dont write PMAO back is a good idea though.
> |
> | > lose interrupts because when the PMU is re-enabled the overflowed values
> | > will cause another interrupt.
>
> Is it enough to set the FC and clear the PMAO - or should we also clear the
> PMAE in pmu_disable() (and set it back in pmu_enable()) ?
Yeah that's on my todo list, I just haven't got around to it. I think
clearing PMAE would be more in keeping with what the HW folks
have in mind, but it's a fairly major change so we'd need to test it
across all supported hardware.
It's not that easy to test because if you miss an interrupt rarely you
will generally not notice it. You'll just see a slightly lower count
for the event which you will just put down to variability.
> The PMU spec says "...Alert will occur when enabled condition or event exists
> and Performance Monitor Alerts are enabled through MMCR0[PMAE] field"
>
> The condition of overflowing counter will still exist and the PMAE is still
> set. So, won't the PMU simply turn PMAO back on after we clear it ?
Not that I've observed. It's not clear to me that the architecture and
the hardware agree 100% on some of these corner cases, but proving it
one way or the other is tricky.
cheers
next prev parent reply other threads:[~2013-07-10 2:12 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-24 11:28 [PATCH 1/8] powerpc/perf: Check that events only include valid bits on Power8 Michael Ellerman
2013-06-24 11:28 ` [PATCH 2/8] powerpc/perf: Rework disable logic in pmu_disable() Michael Ellerman
2013-06-25 11:22 ` Anshuman Khandual
2013-06-26 3:28 ` Michael Ellerman
2013-07-10 0:15 ` Sukadev Bhattiprolu
2013-07-10 2:12 ` Michael Ellerman [this message]
2013-06-24 11:28 ` [PATCH 3/8] powerpc/perf: Freeze PMC5/6 if we're not using them Michael Ellerman
2013-06-24 11:28 ` [PATCH 4/8] powerpc/perf: Use existing out label in power_pmu_enable() Michael Ellerman
2013-06-27 11:01 ` Anshuman Khandual
2013-06-24 11:28 ` [PATCH 5/8] powerpc/perf: Don't enable if we have zero events Michael Ellerman
2013-06-28 5:10 ` Anshuman Khandual
2013-06-24 11:28 ` [PATCH 6/8] powerpc/perf: Drop MMCRA from thread_struct Michael Ellerman
2013-06-24 11:28 ` [PATCH 7/8] powerpc/perf: Core EBB support for 64-bit book3s Michael Ellerman
2013-06-26 8:38 ` Anshuman Khandual
2013-06-27 11:52 ` Michael Ellerman
2013-06-24 11:28 ` [PATCH 8/8] powerpc/perf: Add power8 EBB support Michael Ellerman
2013-06-26 9:58 ` Anshuman Khandual
2013-06-27 11:52 ` Michael Ellerman
2013-06-28 4:15 ` Anshuman Khandual
2013-07-04 18:58 ` Adhemerval Zanella
2013-07-05 2:54 ` Michael Ellerman
2013-07-05 17:57 ` Adhemerval Zanella
2013-06-25 10:55 ` [PATCH 1/8] powerpc/perf: Check that events only include valid bits on Power8 Anshuman Khandual
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20130710021214.GB7491@concordia \
--to=michael@ellerman$(echo .)id.au \
--cc=khandual@linux$(echo .)vnet.ibm.com \
--cc=linuxppc-dev@ozlabs$(echo .)org \
--cc=paulus@samba$(echo .)org \
--cc=sukadev@linux$(echo .)vnet.ibm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox