From: Peter Zijlstra <peterz@infradead•org>
To: Boqun Feng <boqun.feng@gmail•com>
Cc: linux-kernel@vger•kernel.org, linuxppc-dev@lists•ozlabs.org,
Ingo Molnar <mingo@kernel•org>,
Benjamin Herrenschmidt <benh@kernel•crashing.org>,
Paul Mackerras <paulus@samba•org>,
Michael Ellerman <mpe@ellerman•id.au>,
Thomas Gleixner <tglx@linutronix•de>,
Will Deacon <will.deacon@arm•com>,
"Paul E. McKenney" <paulmck@linux•vnet.ibm.com>,
Waiman Long <waiman.long@hp•com>
Subject: Re: [RFC 3/5] powerpc: atomic: implement atomic{,64}_{add,sub}_return_* variants
Date: Fri, 28 Aug 2015 17:39:21 +0200 [thread overview]
Message-ID: <20150828153921.GF19282@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <20150828141602.GA924@fixme-laptop.cn.ibm.com>
On Fri, Aug 28, 2015 at 10:16:02PM +0800, Boqun Feng wrote:
> On Fri, Aug 28, 2015 at 08:06:14PM +0800, Boqun Feng wrote:
> > Hi Peter,
> >
> > On Fri, Aug 28, 2015 at 12:48:54PM +0200, Peter Zijlstra wrote:
> > > On Fri, Aug 28, 2015 at 10:48:17AM +0800, Boqun Feng wrote:
> > > > +/*
> > > > + * Since {add,sub}_return_relaxed and xchg_relaxed are implemented with
> > > > + * a "bne-" instruction at the end, so an isync is enough as a acquire barrier
> > > > + * on the platform without lwsync.
> > > > + */
> > > > +#ifdef CONFIG_SMP
> > > > +#define smp_acquire_barrier__after_atomic() \
> > > > + __asm__ __volatile__(PPC_ACQUIRE_BARRIER : : : "memory")
> > > > +#else
> > > > +#define smp_acquire_barrier__after_atomic() barrier()
> > > > +#endif
> > > > +#define arch_atomic_op_acquire(op, args...) \
> > > > +({ \
> > > > + typeof(op##_relaxed(args)) __ret = op##_relaxed(args); \
> > > > + smp_acquire_barrier__after_atomic(); \
> > > > + __ret; \
> > > > +})
> > > > +
> > > > +#define arch_atomic_op_release(op, args...) \
> > > > +({ \
> > > > + smp_lwsync(); \
> > > > + op##_relaxed(args); \
> > > > +})
> > >
> > > Urgh, so this is RCpc. We were trying to get rid of that if possible.
> > > Lets wait until that's settled before introducing more of it.
> > >
> > > lkml.kernel.org/r/20150820155604.GB24100@arm•com
> >
> > OK, get it. Thanks.
> >
> > So I'm not going to introduce these arch specific macros, I think what I
> > need to implement are just _relaxed variants and cmpxchg_acquire.
>
> Ah.. just read through the thread you mentioned, I might misunderstand
> you, probably because I didn't understand RCpc well..
>
> You are saying that in a RELEASE we -might- switch from smp_lwsync() to
> smp_mb() semantically, right? I guess this means we -might- switch from
> RCpc to RCsc, right?
>
> If so, I think I'd better to wait until we have a conclusion for this.
Yes, the difference between RCpc and RCsc is in the meaning of RELEASE +
ACQUIRE. With RCsc that implies a full memory barrier, with RCpc it does
not.
Currently PowerPC is the only arch that (can, and) does RCpc and gives a
weaker RELEASE + ACQUIRE. Only the CPU who did the ACQUIRE is guaranteed
to see the stores of the CPU which did the RELEASE in order.
As it stands, RCU is the only _known_ codebase where this matters, but
we did in fact write code for a fair number of years 'assuming' RELEASE
+ ACQUIRE was a full barrier, so who knows what else is out there.
RCsc - release consistency sequential consistency
RCpc - release consistency processor consistency
https://en.wikipedia.org/wiki/Processor_consistency (where they have
s/sequential/causal/)
next prev parent reply other threads:[~2015-08-28 15:39 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-28 2:48 [RFC 0/5] atomics: powerpc: implement relaxed/acquire/release variants of some atomics Boqun Feng
2015-08-28 2:48 ` [RFC 1/5] atomics: add test for atomic operations with _relaxed variants Boqun Feng
2015-08-28 2:48 ` [RFC 2/5] atomics: introduce arch_atomic_op_{acquire, release, fence} helpers Boqun Feng
2015-08-28 11:36 ` [RFC 2/5] atomics: introduce arch_atomic_op_{acquire,release,fence} helpers Peter Zijlstra
2015-08-28 11:50 ` Boqun Feng
2015-08-28 2:48 ` [RFC 3/5] powerpc: atomic: implement atomic{, 64}_{add, sub}_return_* variants Boqun Feng
2015-08-28 10:48 ` [RFC 3/5] powerpc: atomic: implement atomic{,64}_{add,sub}_return_* variants Peter Zijlstra
2015-08-28 12:06 ` Boqun Feng
2015-08-28 14:16 ` Boqun Feng
2015-08-28 15:39 ` Peter Zijlstra [this message]
2015-08-28 16:59 ` Boqun Feng
2015-09-01 19:00 ` Will Deacon
2015-09-01 21:45 ` Paul E. McKenney
2015-09-02 9:59 ` Will Deacon
2015-09-02 10:49 ` Paul E. McKenney
2015-09-02 15:23 ` Pranith Kumar
2015-09-02 15:36 ` [RFC 3/5] powerpc: atomic: implement atomic{, 64}_{add, sub}_return_* variants Pranith Kumar
2015-09-03 10:31 ` [RFC 3/5] powerpc: atomic: implement atomic{,64}_{add,sub}_return_* variants Will Deacon
2015-09-11 12:45 ` Will Deacon
2015-09-11 17:09 ` Paul E. McKenney
2015-09-14 11:35 ` Peter Zijlstra
2015-09-14 12:01 ` Peter Zijlstra
2015-09-14 12:11 ` Peter Zijlstra
2015-09-14 15:38 ` Will Deacon
2015-09-14 16:26 ` Paul E. McKenney
2015-08-28 2:48 ` [RFC 4/5] powerpc: atomic: implement xchg_* and atomic{, 64}_xchg_* variants Boqun Feng
2015-08-28 2:48 ` [RFC 5/5] powerpc: atomic: implement cmpxchg{, 64}_* and atomic{, 64}_cmpxchg_* variants Boqun Feng
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