From: Peter Zijlstra <peterz@infradead•org>
To: Will Deacon <will.deacon@arm•com>
Cc: "Paul E. McKenney" <paulmck@linux•vnet.ibm.com>,
Boqun Feng <boqun.feng@gmail•com>,
"linux-kernel@vger•kernel.org" <linux-kernel@vger•kernel.org>,
"linuxppc-dev@lists•ozlabs.org" <linuxppc-dev@lists•ozlabs.org>,
Ingo Molnar <mingo@kernel•org>,
Benjamin Herrenschmidt <benh@kernel•crashing.org>,
Paul Mackerras <paulus@samba•org>,
Michael Ellerman <mpe@ellerman•id.au>,
Thomas Gleixner <tglx@linutronix•de>,
Waiman Long <waiman.long@hp•com>
Subject: Re: [RFC 3/5] powerpc: atomic: implement atomic{,64}_{add,sub}_return_* variants
Date: Mon, 14 Sep 2015 14:01:53 +0200 [thread overview]
Message-ID: <20150914120153.GY18673@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <20150914113520.GP18489@twins.programming.kicks-ass.net>
On Mon, Sep 14, 2015 at 01:35:20PM +0200, Peter Zijlstra wrote:
>
> Sorry for being tardy, I had a wee spell of feeling horrible and then I
> procrastinated longer than I should have.
>
> On Fri, Sep 11, 2015 at 01:45:07PM +0100, Will Deacon wrote:
>
> > Peter, any thoughts? I'm not au fait with the x86 memory model, but what
> > Paul's saying is worrying.
>
> Right, so Paul is right -- and I completely forgot (I used to know about
> that).
>
> So all the TSO archs (SPARC-TSO, x86 (!OOSTORE) and s390) can do
> smp_load_acquire()/smp_store_release() with just barrier(), and while:
>
> smp_store_release(&x);
> smp_load_acquire(&x);
>
> will provide full order by means of the address dependency,
>
> smp_store_release(&x);
> smp_load_acquire(&y);
>
> will not. Because the one reorder TSO allows is exactly that one.
>
> > Peter -- if the above reordering can happen on x86, then moving away
> > from RCpc is going to be less popular than I hoped...
>
> Sadly yes.. We could of course try and split LOCK from ACQUIRE again,
> but I'm not sure that's going to help anything except confusion.
This of course also means we need something like:
smp_mb__release_acquire()
which cannot be a no-op for TSO archs. And it might even mean it needs
to be the same as smp_mb__unlock_lock(), but I need to think more on
this.
The scenario is:
CPU0 CPU1
unlock(x)
smp_store_release(&x->lock, 0);
unlock(y)
smp_store_release(&next->lock, 1); /* next == &y */
lock(y)
while (!(smp_load_acquire(&y->lock))
cpu_relax();
Where the lock does _NOT_ issue a store to acquire the lock at all. Now
I don't think any of our current primitives manage this, so we should be
good, but it might just be possible.
And at the same time; having both:
smp_mb__release_acquire()
smp_mb__unlock_lock()
is quite horrible, for it clearly shows a LOCK isn't quite the same as
ACQUIRE :/
next prev parent reply other threads:[~2015-09-14 12:02 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-28 2:48 [RFC 0/5] atomics: powerpc: implement relaxed/acquire/release variants of some atomics Boqun Feng
2015-08-28 2:48 ` [RFC 1/5] atomics: add test for atomic operations with _relaxed variants Boqun Feng
2015-08-28 2:48 ` [RFC 2/5] atomics: introduce arch_atomic_op_{acquire, release, fence} helpers Boqun Feng
2015-08-28 11:36 ` [RFC 2/5] atomics: introduce arch_atomic_op_{acquire,release,fence} helpers Peter Zijlstra
2015-08-28 11:50 ` Boqun Feng
2015-08-28 2:48 ` [RFC 3/5] powerpc: atomic: implement atomic{, 64}_{add, sub}_return_* variants Boqun Feng
2015-08-28 10:48 ` [RFC 3/5] powerpc: atomic: implement atomic{,64}_{add,sub}_return_* variants Peter Zijlstra
2015-08-28 12:06 ` Boqun Feng
2015-08-28 14:16 ` Boqun Feng
2015-08-28 15:39 ` Peter Zijlstra
2015-08-28 16:59 ` Boqun Feng
2015-09-01 19:00 ` Will Deacon
2015-09-01 21:45 ` Paul E. McKenney
2015-09-02 9:59 ` Will Deacon
2015-09-02 10:49 ` Paul E. McKenney
2015-09-02 15:23 ` Pranith Kumar
2015-09-02 15:36 ` [RFC 3/5] powerpc: atomic: implement atomic{, 64}_{add, sub}_return_* variants Pranith Kumar
2015-09-03 10:31 ` [RFC 3/5] powerpc: atomic: implement atomic{,64}_{add,sub}_return_* variants Will Deacon
2015-09-11 12:45 ` Will Deacon
2015-09-11 17:09 ` Paul E. McKenney
2015-09-14 11:35 ` Peter Zijlstra
2015-09-14 12:01 ` Peter Zijlstra [this message]
2015-09-14 12:11 ` Peter Zijlstra
2015-09-14 15:38 ` Will Deacon
2015-09-14 16:26 ` Paul E. McKenney
2015-08-28 2:48 ` [RFC 4/5] powerpc: atomic: implement xchg_* and atomic{, 64}_xchg_* variants Boqun Feng
2015-08-28 2:48 ` [RFC 5/5] powerpc: atomic: implement cmpxchg{, 64}_* and atomic{, 64}_cmpxchg_* variants Boqun Feng
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