From: Simon Guo <wei.guo.simon@gmail•com>
To: Cyril Bur <cyrilbur@gmail•com>
Cc: linuxppc-dev@lists•ozlabs.org, mpe@ellerman•id.au,
mikey@neuling•org, anton@samba•org
Subject: Re: [PATCH 2/2] powerpc: tm: Enable transactional memory (TM) lazily for userspace
Date: Mon, 19 Sep 2016 12:47:19 +0800 [thread overview]
Message-ID: <20160919044718.GB3797@simonLocalRHEL7.x64> (raw)
In-Reply-To: <20160914080216.13833-3-cyrilbur@gmail.com>
On Wed, Sep 14, 2016 at 06:02:16PM +1000, Cyril Bur wrote:
> @@ -954,8 +963,16 @@ static inline void __switch_to_tm(struct task_struct *prev,
> struct task_struct *new)
> {
> if (cpu_has_feature(CPU_FTR_TM)) {
> - tm_enable();
> - tm_reclaim_task(prev);
> + if (tm_enabled(prev) || tm_enabled(new))
> + tm_enable();
> +
> + if (tm_enabled(prev)) {
> + prev->thread.load_tm++;
> + tm_reclaim_task(prev);
> + if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0)
> + prev->thread.regs->msr &= ~MSR_TM;
> + }
Hi Cyril,
If MSR_TM_ACTIVE(), is it better to reset load_tm to 0?
Other looks good to me.
Thanks,
- Simon
next prev parent reply other threads:[~2016-09-19 4:47 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-14 8:02 [PATCH 0/2] Enable MSR_TM lazily Cyril Bur
2016-09-14 8:02 ` [PATCH 1/2] powerpc: tm: Add TM Unavailable Exception Cyril Bur
2016-10-05 2:36 ` [1/2] " Michael Ellerman
2016-09-14 8:02 ` [PATCH 2/2] powerpc: tm: Enable transactional memory (TM) lazily for userspace Cyril Bur
2016-09-19 4:47 ` Simon Guo [this message]
2016-09-19 5:26 ` Cyril Bur
2016-09-14 11:28 ` [PATCH 0/2] Enable MSR_TM lazily Nicholas Piggin
2016-09-14 11:46 ` Michael Neuling
2016-09-14 12:12 ` Nicholas Piggin
2016-09-14 12:17 ` Michael Neuling
2016-09-14 14:10 ` Carlos Eduardo Seo
2016-09-15 3:59 ` Nicholas Piggin
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