Subject: [PATCH] powerpc/powernv: Fix SMT4 forcing idle code

From: Nicholas Piggin <[email-masked]>
Date: Sun, 1 Apr 2018 15:38:13 +1000

PSSCR value is not stored to PACA_REQ_PSSCR in case the CPU does
not have the XER[SO] bug.

Fix this by storing up-front, outside the workaround code. The
initial test is not required because it is a slow path.

The workaround is made to depend on CONFIG_KVM_BOOK3S_HV_POSSIBLE, to
match pnv_power9_force_smt4_catch() where it is used.

Fixes: 7672691a08 ("powerpc/powernv: Provide a way to force a core into SMT4 mode")
Cc: Paul Mackerras <[email-masked]>
Signed-off-by: Nicholas Piggin <[email-masked]>
---
 arch/powerpc/kernel/idle_book3s.S | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/kernel/idle_book3s.S b/arch/powerpc/kernel/idle_book3s.S
index 89157cf452e3..d503203842b0 100644
--- a/arch/powerpc/kernel/idle_book3s.S
+++ b/arch/powerpc/kernel/idle_book3s.S
@@ -430,20 +430,20 @@ ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66);		\
  * r3 contains desired PSSCR register value.
  */
 _GLOBAL(power9_idle_stop)
-BEGIN_FTR_SECTION
-	lwz	r5, PACA_DONT_STOP(r13)
-	cmpwi	r5, 0
-	bne	1f
 	std	r3, PACA_REQ_PSSCR(r13)
+#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
+BEGIN_FTR_SECTION
 	sync
 	lwz	r5, PACA_DONT_STOP(r13)
 	cmpwi	r5, 0
 	bne	1f
 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
+#endif
 	mtspr 	SPRN_PSSCR,r3
 	LOAD_REG_ADDR(r4,power_enter_stop)
 	b	pnv_powersave_common
 	/* No return */
+#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
 1:
 	/*
 	 * We get here when TM / thread reconfiguration bug workaround
@@ -453,6 +453,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
 	li	r3, 0
 	std	r3, PACA_REQ_PSSCR(r13)
 	blr		/* return 0 for wakeup cause / SRR1 value */
+#endif
 
 /*
  * On waking up from stop 0,1,2 with ESL=1 on POWER9 DD1,
-- 
2.16.3