From: Claudio Carvalho <cclaudio@linux•ibm.com>
To: Paul Mackerras <paulus@ozlabs•org>,
Michael Ellerman <mpe@ellerman•id.au>,
kvm-ppc@vger•kernel.org, linuxppc-dev@ozlabs•org
Cc: Madhavan Srinivasan <maddy@linux•vnet.ibm.com>,
Michael Anderson <andmike@linux•ibm.com>,
Ram Pai <linuxram@us•ibm.com>,
Bharata B Rao <bharata@linux•ibm.com>,
Sukadev Bhattiprolu <sukadev@linux•vnet.ibm.com>,
Thiago Jung Bauermann <bauerman@linux•ibm.com>,
Anshuman Khandual <khandual@linux•vnet.ibm.com>
Subject: [RFC PATCH v2 02/10] KVM: PPC: Ultravisor: Introduce the MSR_S bit
Date: Sat, 18 May 2019 11:25:16 -0300 [thread overview]
Message-ID: <20190518142524.28528-3-cclaudio@linux.ibm.com> (raw)
In-Reply-To: <20190518142524.28528-1-cclaudio@linux.ibm.com>
From: Sukadev Bhattiprolu <sukadev@linux•vnet.ibm.com>
The ultravisor processor mode is introduced in POWER platforms that
supports the Protected Execution Facility (PEF). Ultravisor is higher
privileged than hypervisor mode.
In PEF enabled platforms, the MSR_S bit is used to indicate if the
thread is in secure state. With the MSR_S bit, the privilege state of
the thread is now determined by MSR_S, MSR_HV and MSR_PR, as follows:
S HV PR
-----------------------
0 x 1 problem
1 0 1 problem
x x 0 privileged
x 1 0 hypervisor
1 1 0 ultravisor
1 1 1 reserved
The hypervisor doesn't (and can't) run with the MSR_S bit set, but a
secure guest and the ultravisor firmware do.
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux•vnet.ibm.com>
Signed-off-by: Ram Pai <linuxram@us•ibm.com>
[Update the commit message]
Signed-off-by: Claudio Carvalho <cclaudio@linux•ibm.com>
---
arch/powerpc/include/asm/reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 10caa145f98b..39b4c0a519f5 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -38,6 +38,7 @@
#define MSR_TM_LG 32 /* Trans Mem Available */
#define MSR_VEC_LG 25 /* Enable AltiVec */
#define MSR_VSX_LG 23 /* Enable VSX */
+#define MSR_S_LG 22 /* Secure VM bit */
#define MSR_POW_LG 18 /* Enable Power Management */
#define MSR_WE_LG 18 /* Wait State Enable */
#define MSR_TGPR_LG 17 /* TLB Update registers in use */
@@ -71,11 +72,13 @@
#define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */
#define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */
#define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */
+#define MSR_S __MASK(MSR_S_LG) /* Secure state */
#else
/* so tests for these bits fail on 32-bit */
#define MSR_SF 0
#define MSR_ISF 0
#define MSR_HV 0
+#define MSR_S 0
#endif
/*
--
2.20.1
next prev parent reply other threads:[~2019-05-18 14:29 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-18 14:25 [RFC PATCH v2 00/10] kvmppc: Paravirtualize KVM to support ultravisor Claudio Carvalho
2019-05-18 14:25 ` [RFC PATCH v2 01/10] KVM: PPC: Ultravisor: Add PPC_UV config option Claudio Carvalho
2019-05-18 14:25 ` Claudio Carvalho [this message]
2019-05-18 14:25 ` [RFC PATCH v2 03/10] powerpc: Introduce FW_FEATURE_ULTRAVISOR Claudio Carvalho
2019-05-18 14:25 ` [RFC PATCH v2 04/10] KVM: PPC: Ultravisor: Add generic ultravisor call handler Claudio Carvalho
2019-05-18 14:25 ` [RFC PATCH v2 05/10] KVM: PPC: Ultravisor: Use UV_WRITE_PATE ucall to register a PATE Claudio Carvalho
2019-05-18 14:25 ` [RFC PATCH v2 06/10] KVM: PPC: Ultravisor: Restrict flush of the partition tlb cache Claudio Carvalho
2019-05-18 14:25 ` [RFC PATCH v2 07/10] KVM: PPC: Ultravisor: Restrict LDBAR access Claudio Carvalho
2019-05-20 5:43 ` Paul Mackerras
2019-05-21 5:24 ` Madhavan Srinivasan
2019-05-30 22:51 ` Claudio Carvalho
2019-05-18 14:25 ` [RFC PATCH v2 08/10] KVM: PPC: Ultravisor: Return to UV for hcalls from SVM Claudio Carvalho
2019-05-20 6:17 ` Paul Mackerras
2019-05-18 14:25 ` [RFC PATCH v2 09/10] KVM: PPC: Book3S HV: Fixed for running secure guests Claudio Carvalho
2019-05-20 6:40 ` Paul Mackerras
2019-05-18 14:25 ` [RFC PATCH v2 10/10] KVM: PPC: Ultravisor: Check for MSR_S during hv_reset_msr Claudio Carvalho
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