Subject: Re: [PATCH 1/2] powerpc/pseries/svm: Don't access some SPRs

From: Sukadev Bhattiprolu <[email-masked]>
Date: Wed, 18 Dec 2019 15:57:53 -0800

Michael Ellerman [[email-masked]] wrote:
> 
> eg. here.
> 
> This is the fast path of context switch.
> 
> That expands to:
> 
> 	if (!(mfmsr() & MSR_S))
> 		asm volatile("mfspr %0, SPRN_BESCR" : "=r" (rval));
> 	if (!(mfmsr() & MSR_S))
> 		asm volatile("mfspr %0, SPRN_EBBHR" : "=r" (rval));
> 	if (!(mfmsr() & MSR_S))
> 		asm volatile("mfspr %0, SPRN_EBBRR" : "=r" (rval));
> 

Yes, should have optimized this at least :-)
> 
> If the Ultravisor is going to disable EBB and BHRB then we need new
> CPU_FTR bits for those, and the code that accesses those registers
> needs to be put behind cpu_has_feature(EBB) etc.

Will try the cpu_has_feature(). Would it be ok to use a single feature
bit, like UV or make it per-register group as that could need more
feature bits?

Thanks,

Sukadev