From: Nicholas Piggin <npiggin@gmail•com>
To: linuxppc-dev@lists•ozlabs.org
Cc: "Aneesh Kumar K.V" <aneesh.kumar@linux•ibm.com>,
Paul Mackerras <paulus@samba•org>,
Nicholas Piggin <npiggin@gmail•com>,
Milton Miller <miltonm@us•ibm.com>
Subject: [PATCH 2/4] powerpc/64s/pseries: Fix hash tlbiel_all_isa300 for guest kernels
Date: Thu, 26 Nov 2020 20:25:28 +1000 [thread overview]
Message-ID: <20201126102530.691335-3-npiggin@gmail.com> (raw)
In-Reply-To: <20201126102530.691335-1-npiggin@gmail.com>
tlbiel_all() can not be usable in !HVMODE when running hash presently,
remove HV privileged flushes when running in guest to make it usable.
Signed-off-by: Nicholas Piggin <npiggin@gmail•com>
---
arch/powerpc/mm/book3s64/hash_native.c | 21 ++++++++++++++-------
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/mm/book3s64/hash_native.c b/arch/powerpc/mm/book3s64/hash_native.c
index 97fa42d7027e..52e170bd95ae 100644
--- a/arch/powerpc/mm/book3s64/hash_native.c
+++ b/arch/powerpc/mm/book3s64/hash_native.c
@@ -92,16 +92,15 @@ static void tlbiel_all_isa300(unsigned int num_sets, unsigned int is)
asm volatile("ptesync": : :"memory");
/*
- * Flush the first set of the TLB, and any caching of partition table
- * entries. Then flush the remaining sets of the TLB. Hash mode uses
- * partition scoped TLB translations.
+ * Flush the partition table cache if this is HV mode.
*/
- tlbiel_hash_set_isa300(0, is, 0, 2, 0);
- for (set = 1; set < num_sets; set++)
- tlbiel_hash_set_isa300(set, is, 0, 0, 0);
+ if (early_cpu_has_feature(CPU_FTR_HVMODE))
+ tlbiel_hash_set_isa300(0, is, 0, 2, 0);
/*
- * Now invalidate the process table cache.
+ * Now invalidate the process table cache. UPRT=0 HPT modes (what
+ * current hardware implements) do not use the process table, but
+ * add the flushes anyway.
*
* From ISA v3.0B p. 1078:
* The following forms are invalid.
@@ -110,6 +109,14 @@ static void tlbiel_all_isa300(unsigned int num_sets, unsigned int is)
*/
tlbiel_hash_set_isa300(0, is, 0, 2, 1);
+ /*
+ * Then flush the sets of the TLB proper. Hash mode uses
+ * partition scoped TLB translations, which may be flushed
+ * in !HV mode.
+ */
+ for (set = 0; set < num_sets; set++)
+ tlbiel_hash_set_isa300(set, is, 0, 0, 0);
+
ppc_after_tlbiel_barrier();
asm volatile(PPC_ISA_3_0_INVALIDATE_ERAT "; isync" : : :"memory");
--
2.23.0
next prev parent reply other threads:[~2020-11-26 10:30 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-26 10:25 [PATCH 0/4] powerpc/64s: Fix for radix TLB invalidation bug Nicholas Piggin
2020-11-26 10:25 ` [PATCH 1/4] powerpc/64s: Fix hash ISA v3.0 TLBIEL instruction generation Nicholas Piggin
2020-11-26 10:25 ` Nicholas Piggin [this message]
2020-11-26 10:25 ` [PATCH 3/4] kernel/cpu: add arch override for clear_tasks_mm_cpumask() mm handling Nicholas Piggin
2020-11-26 10:25 ` [PATCH 4/4] powerpc/64s: Trim offlined CPUs from mm_cpumasks Nicholas Piggin
2020-11-26 10:36 ` [PATCH 0/4] powerpc/64s: Fix for radix TLB invalidation bug Aneesh Kumar K.V
2020-12-04 11:59 ` Michael Ellerman
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