From: Gautham R Shenoy <ego@linux•vnet.ibm.com>
To: Srikar Dronamraju <srikar@linux•vnet.ibm.com>
Cc: Nathan Lynch <nathanl@linux•ibm.com>,
"Gautham R. Shenoy" <ego@linux•vnet.ibm.com>,
Michael Neuling <mikey@neuling•org>,
Vaidyanathan Srinivasan <svaidy@linux•vnet.ibm.com>,
Peter Zijlstra <peterz@infradead•org>,
linux-kernel@vger•kernel.org, Nicholas Piggin <npiggin@gmail•com>,
linuxppc-dev@lists•ozlabs.org,
Valentin Schneider <valentin.schneider@arm•com>
Subject: Re: [PATCH 3/3] powerpc/cacheinfo: Print correct cache-sibling map/list for L2 cache
Date: Tue, 8 Dec 2020 23:26:47 +0530 [thread overview]
Message-ID: <20201208175647.GC14206@in.ibm.com> (raw)
In-Reply-To: <20201207131138.GJ528281@linux.vnet.ibm.com>
On Mon, Dec 07, 2020 at 06:41:38PM +0530, Srikar Dronamraju wrote:
> * Gautham R. Shenoy <ego@linux•vnet.ibm.com> [2020-12-04 10:18:47]:
>
> > From: "Gautham R. Shenoy" <ego@linux•vnet.ibm.com>
> >
> >
> > Signed-off-by: Gautham R. Shenoy <ego@linux•vnet.ibm.com>
> > ---
> >
> > +extern bool thread_group_shares_l2;
> > /*
> > * On big-core systems, each core has two groups of CPUs each of which
> > * has its own L1-cache. The thread-siblings which share l1-cache with
> > * @cpu can be obtained via cpu_smallcore_mask().
> > + *
> > + * On some big-core systems, the L2 cache is shared only between some
> > + * groups of siblings. This is already parsed and encoded in
> > + * cpu_l2_cache_mask().
> > */
> > static const struct cpumask *get_big_core_shared_cpu_map(int cpu, struct cache *cache)
> > {
> > if (cache->level == 1)
> > return cpu_smallcore_mask(cpu);
> > + if (cache->level == 2 && thread_group_shares_l2)
> > + return cpu_l2_cache_mask(cpu);
> >
> > return &cache->shared_cpu_map;
>
> As pointed with lkp@intel•org, we need to do this only with #CONFIG_SMP,
> even for cache->level = 1 too.
Yes, I have fixed that in the next version.
>
> I agree that we are displaying shared_cpu_map correctly. Should we have also
> update /clear shared_cpu_map in the first place. For example:- If for a P9
> core with CPUs 0-7, the cache->shared_cpu_map for L1 would have 0-7 but
> would display 0,2,4,6.
>
> The drawback of this is even if cpus 0,2,4,6 are released L1 cache will not
> be released. Is this as expected?
cacheinfo populates the cache->shared_cpu_map on the basis of which
CPUs share the common device-tree node for a particular cache. There
is one l1-cache object in the device-tree for a CPU node corresponding
to a big-core. That the L1 is further split between the threads of the
core is shown using ibm,thread-groups.
The ideal thing would be to add a "group_leader" field to "struct
cache" so that we can create separate cache objects , one per thread
group. I will take a stab at this in the v2.
Thanks for the review comments.
>
>
> --
> Thanks and Regards
> Srikar Dronamraju
next prev parent reply other threads:[~2020-12-08 17:58 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-04 4:48 [PATCH 0/3] Extend Parsing "ibm, thread-groups" for Shared-L2 information Gautham R. Shenoy
2020-12-04 4:48 ` [PATCH 1/3] powerpc/smp: Parse ibm, thread-groups with multiple properties Gautham R. Shenoy
2020-12-07 12:10 ` [PATCH 1/3] powerpc/smp: Parse ibm,thread-groups " Srikar Dronamraju
2020-12-08 17:25 ` Gautham R Shenoy
2020-12-09 3:59 ` [PATCH 1/3] powerpc/smp: Parse ibm, thread-groups " Michael Ellerman
2020-12-09 8:35 ` [PATCH 1/3] powerpc/smp: Parse ibm,thread-groups " Srikar Dronamraju
2020-12-09 9:05 ` Gautham R Shenoy
2020-12-04 4:48 ` [PATCH 2/3] powerpc/smp: Add support detecting thread-groups sharing L2 cache Gautham R. Shenoy
2020-12-07 12:40 ` Srikar Dronamraju
2020-12-08 17:42 ` Gautham R Shenoy
2020-12-09 9:14 ` Srikar Dronamraju
2020-12-04 4:48 ` [PATCH 3/3] powerpc/cacheinfo: Print correct cache-sibling map/list for " Gautham R. Shenoy
2020-12-07 13:11 ` Srikar Dronamraju
2020-12-08 17:56 ` Gautham R Shenoy [this message]
2020-12-09 8:39 ` Srikar Dronamraju
2020-12-09 9:07 ` Gautham R Shenoy
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