From: Kajol Jain <kjain@linux•ibm.com>
To: mpe@ellerman•id.au, linuxppc-dev@lists•ozlabs.org,
linux-kernel@vger•kernel.org, peterz@infradead•org,
mingo@redhat•com, acme@kernel•org, jolsa@kernel•org,
namhyung@kernel•org, linux-perf-users@vger•kernel.org,
ak@linux•intel.com
Cc: mark.rutland@arm•com, songliubraving@fb•com,
atrajeev@linux•vnet.ibm.com, daniel@iogearbox•net,
rnsastry@linux•ibm.com, alexander.shishkin@linux•intel.com,
kjain@linux•ibm.com, ast@kernel•org, yao.jin@linux•intel.com,
maddy@linux•ibm.com, paulus@samba•org, kan.liang@linux•intel.com
Subject: [PATCH 2/3] perf: Add macros to specify onchip L2/L3 accesses
Date: Sat, 4 Sep 2021 12:19:31 +0530 [thread overview]
Message-ID: <20210904064932.307610-2-kjain@linux.ibm.com> (raw)
In-Reply-To: <20210904064932.307610-1-kjain@linux.ibm.com>
Add couple of new macros to represent onchip L2 and onchip L3 accesses.
Patch also adds the decoding strings in the mem_lvlnum data structure.
Signed-off-by: Kajol Jain <kjain@linux•ibm.com>
---
tools/include/uapi/linux/perf_event.h | 4 +++-
tools/perf/util/mem-events.c | 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/tools/include/uapi/linux/perf_event.h b/tools/include/uapi/linux/perf_event.h
index f92880a15645..030b3e990ac3 100644
--- a/tools/include/uapi/linux/perf_event.h
+++ b/tools/include/uapi/linux/perf_event.h
@@ -1265,7 +1265,9 @@ union perf_mem_data_src {
#define PERF_MEM_LVLNUM_L2 0x02 /* L2 */
#define PERF_MEM_LVLNUM_L3 0x03 /* L3 */
#define PERF_MEM_LVLNUM_L4 0x04 /* L4 */
-/* 5-0xa available */
+#define PERF_MEM_LVLNUM_OC_L2 0x05 /* On Chip L2 */
+#define PERF_MEM_LVLNUM_OC_L3 0x06 /* On Chip L3 */
+/* 7-0xa available */
#define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */
#define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */
#define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */
diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c
index f0e75df72b80..f846a91220c2 100644
--- a/tools/perf/util/mem-events.c
+++ b/tools/perf/util/mem-events.c
@@ -294,6 +294,8 @@ static const char * const mem_lvl[] = {
};
static const char * const mem_lvlnum[] = {
+ [PERF_MEM_LVLNUM_OC_L2] = "OnChip L2",
+ [PERF_MEM_LVLNUM_OC_L3] = "OnChip L3",
[PERF_MEM_LVLNUM_ANY_CACHE] = "Any cache",
[PERF_MEM_LVLNUM_LFB] = "LFB",
[PERF_MEM_LVLNUM_RAM] = "RAM",
--
2.26.2
next prev parent reply other threads:[~2021-09-04 6:52 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-04 6:49 [PATCH 1/3] perf: Add macros to specify onchip L2/L3 accesses Kajol Jain
2021-09-04 6:49 ` Kajol Jain [this message]
2021-09-04 6:49 ` [PATCH 3/3] powerpc/perf: Fix data source encodings for power10 Kajol Jain
2021-09-08 7:17 ` [PATCH 1/3] perf: Add macros to specify onchip L2/L3 accesses Michael Ellerman
2021-09-08 9:26 ` Peter Zijlstra
2021-09-09 12:45 ` Michael Ellerman
2021-09-09 14:36 ` Peter Zijlstra
2021-09-14 10:40 ` Michael Ellerman
2021-09-14 11:49 ` Peter Zijlstra
2021-09-16 10:57 ` Michael Ellerman
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