From: Rob Herring <robh@kernel•org>
To: Shengjiu Wang <shengjiu.wang@nxp•com>
Cc: devicetree@vger•kernel.org, alsa-devel@alsa-project•org,
linuxppc-dev@lists•ozlabs.org, Xiubo.Lee@gmail•com,
festevam@gmail•com, tiwai@suse•com, lgirdwood@gmail•com,
perex@perex•cz, nicoleotsuka@gmail•com, broonie@kernel•org,
krzk+dt@kernel•org, shengjiu.wang@gmail•com,
linux-kernel@vger•kernel.org
Subject: Re: [PATCH v2 6/7] ASoC: dt-bindings: fsl-sai: Add new property to configure dataline
Date: Mon, 27 Jun 2022 17:00:12 -0600 [thread overview]
Message-ID: <20220627230012.GA3122063-robh@kernel.org> (raw)
In-Reply-To: <1655451877-16382-7-git-send-email-shengjiu.wang@nxp.com>
On Fri, Jun 17, 2022 at 03:44:36PM +0800, Shengjiu Wang wrote:
> "fsl,dataline" is added to configure the dataline of SAI.
> It has 3 value for each configuration, first one means the type:
> I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is
> dataline mask for 'tx'. for example:
>
> fsl,dataline = <1 0xff 0xff 2 0xff 0x11>,
>
> it means I2S type rx mask is 0xff, tx mask is 0xff, PDM type
> rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled).
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp•com>
> ---
> Documentation/devicetree/bindings/sound/fsl-sai.txt | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt
> index c71c5861d787..4c66e6a1a533 100644
> --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt
> +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt
> @@ -49,6 +49,14 @@ Required properties:
> receive data by following their own bit clocks and
> frame sync clocks separately.
>
> + - fsl,dataline : configure the dataline. it has 3 value for each configuration
> + first one means the type: I2S(1) or PDM(2)
> + second one is dataline mask for 'rx'
> + third one is dataline mask for 'tx'.
> + for example: fsl,dataline = <1 0xff 0xff 2 0xff 0x11>;
> + it means I2S type rx mask is 0xff, tx mask is 0xff, PDM type
> + rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled).
You mean 0 and 4 enabled? Or 1 and 4?
How many 3 cell entries can you have?
Rob
next prev parent reply other threads:[~2022-06-27 23:00 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-17 7:44 [PATCH v2 0/7] Add PDM/DSD/dataline configuration support Shengjiu Wang
2022-06-17 7:44 ` [PATCH v2 1/7] ASoC: fsl_sai: Add PDM daifmt support Shengjiu Wang
2022-06-17 7:44 ` [PATCH v2 2/7] ASoC: fsl_sai: Add DSD bit format support Shengjiu Wang
2022-06-17 7:44 ` [PATCH v2 3/7] ASoC: fsl_sai: Add support for more sample rates Shengjiu Wang
2022-06-17 7:44 ` [PATCH v2 4/7] ASoc: fsl_sai: Add pinctrl operation for PDM and DSD Shengjiu Wang
2022-06-17 7:44 ` [PATCH v2 5/7] ASoC: fsl_sai: Make res a member of struct fsl_sai Shengjiu Wang
2022-06-17 7:44 ` [PATCH v2 6/7] ASoC: dt-bindings: fsl-sai: Add new property to configure dataline Shengjiu Wang
2022-06-27 23:00 ` Rob Herring [this message]
2022-06-28 2:23 ` Shengjiu Wang
2022-06-17 7:44 ` [PATCH v2 7/7] ASoC: fsl_sai: Configure dataline/FIFO information from dts property Shengjiu Wang
2022-06-28 10:31 ` [PATCH v2 0/7] Add PDM/DSD/dataline configuration support Mark Brown
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