From: Puranjay Mohan <puranjay12@gmail•com>
To: Alexei Starovoitov <ast@kernel•org>,
Daniel Borkmann <daniel@iogearbox•net>,
Andrii Nakryiko <andrii@kernel•org>,
Martin KaFai Lau <martin.lau@linux•dev>,
Song Liu <song@kernel•org>,
Yonghong Song <yonghong.song@linux•dev>,
John Fastabend <john.fastabend@gmail•com>,
KP Singh <kpsingh@kernel•org>,
Stanislav Fomichev <sdf@google•com>, Hao Luo <haoluo@google•com>,
Jiri Olsa <jolsa@kernel•org>,
Shubham Bansal <illusionist.neo@gmail•com>,
Russell King <linux@armlinux•org.uk>,
"James E.J. Bottomley" <James.Bottomley@HansenPartnership•com>,
Helge Deller <deller@gmx•de>,
"Naveen N. Rao" <naveen.n.rao@linux•ibm.com>,
Michael Ellerman <mpe@ellerman•id.au>,
Nicholas Piggin <npiggin@gmail•com>,
Christophe Leroy <christophe.leroy@csgroup•eu>,
Luke Nelson <luke.r.nels@gmail•com>, Xi Wang <xi.wang@gmail•com>,
Paul Walmsley <paul.walmsley@sifive•com>,
Palmer Dabbelt <palmer@dabbelt•com>,
Albert Ou <aou@eecs•berkeley.edu>,
Wang YanQing <udknight@gmail•com>,
bpf@vger•kernel.org, linux-arm-kernel@lists•infradead.org,
linux-kernel@vger•kernel.org, linux-parisc@vger•kernel.org,
linuxppc-dev@lists•ozlabs.org, linux-riscv@lists•infradead.org,
netdev@vger•kernel.org
Cc: puranjay12@gmail•com
Subject: [PATCH bpf-next 4/6] bpf, powerpc32: Always zero extend for LDX
Date: Tue, 12 Sep 2023 22:46:52 +0000 [thread overview]
Message-ID: <20230912224654.6556-5-puranjay12@gmail.com> (raw)
In-Reply-To: <20230912224654.6556-1-puranjay12@gmail.com>
The JITs should not depend on the verifier for zero extending the upper
32 bits of the destination register when loading a byte, half-word, or
word.
A following patch will make the verifier stop patching zext instructions
after LDX.
Signed-off-by: Puranjay Mohan <puranjay12@gmail•com>
---
arch/powerpc/net/bpf_jit_comp32.c | 25 ++++++++-----------------
1 file changed, 8 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/net/bpf_jit_comp32.c b/arch/powerpc/net/bpf_jit_comp32.c
index 7f91ea064c08..0a952a2cfaac 100644
--- a/arch/powerpc/net/bpf_jit_comp32.c
+++ b/arch/powerpc/net/bpf_jit_comp32.c
@@ -936,14 +936,13 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *
PPC_BCC_SHORT(COND_GT, (ctx->idx + 4) * 4);
EMIT(PPC_RAW_LI(dst_reg, 0));
/*
- * For BPF_DW case, "li reg_h,0" would be needed when
- * !fp->aux->verifier_zext. Emit NOP otherwise.
+ * For BPF_DW case, "li reg_h,0" would be needed emit NOP otherwise.
*
* Note that "li reg_h,0" is emitted for BPF_B/H/W case,
* if necessary. So, jump there insted of emitting an
* additional "li reg_h,0" instruction.
*/
- if (size == BPF_DW && !fp->aux->verifier_zext)
+ if (size == BPF_DW)
EMIT(PPC_RAW_LI(dst_reg_h, 0));
else
EMIT(PPC_RAW_NOP());
@@ -974,7 +973,7 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *
break;
}
- if (size != BPF_DW && !fp->aux->verifier_zext)
+ if (size != BPF_DW)
EMIT(PPC_RAW_LI(dst_reg_h, 0));
if (BPF_MODE(code) == BPF_PROBE_MEM) {
@@ -982,20 +981,12 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *
int jmp_off = 4;
/*
- * In case of BPF_DW, two lwz instructions are emitted, one
- * for higher 32-bit and another for lower 32-bit. So, set
- * ex->insn to the first of the two and jump over both
- * instructions in fixup.
- *
- * Similarly, with !verifier_zext, two instructions are
- * emitted for BPF_B/H/W case. So, set ex->insn to the
- * instruction that could fault and skip over both
- * instructions.
+ * Two instructions are emitted for LDX.
+ * So, set ex->insn to the instruction that could fault and skip
+ * over both instructions.
*/
- if (size == BPF_DW || !fp->aux->verifier_zext) {
- insn_idx -= 1;
- jmp_off += 4;
- }
+ insn_idx -= 1;
+ jmp_off += 4;
ret = bpf_add_extable_entry(fp, image, pass, ctx, insn_idx,
jmp_off, dst_reg);
--
2.39.2
next prev parent reply other threads:[~2023-09-12 22:51 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-12 22:46 [PATCH bpf-next 0/6] bpf: verifier: stop emitting zext for LDX Puranjay Mohan
2023-09-12 22:46 ` [PATCH bpf-next 1/6] bpf, riscv32: Always zero extend for LDX with B/W/H Puranjay Mohan
2023-09-12 22:46 ` [PATCH bpf-next 2/6] bpf, x86-32: " Puranjay Mohan
2023-09-12 22:46 ` [PATCH bpf-next 3/6] bpf, parisc32: " Puranjay Mohan
2023-09-12 22:46 ` Puranjay Mohan [this message]
2023-09-12 22:46 ` [PATCH bpf-next 5/6] bpf, arm32: Always zero extend for LDX with B/H/W Puranjay Mohan
2023-09-12 23:03 ` Russell King (Oracle)
2023-09-12 23:16 ` Puranjay Mohan
2023-09-13 0:10 ` Alexei Starovoitov
2023-09-12 22:46 ` [PATCH bpf-next 6/6] bpf, verifier: always mark destination of LDX as 64-bit Puranjay Mohan
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