From: "Gerhard Pircher" <gerhard_pircher@gmx•net>
To: Benjamin Herrenschmidt <benh@kernel•crashing.org>
Cc: linuxppc-dev@ozlabs•org, debian-powerpc@lists•debian.org
Subject: Re: Not coherent cache DMA for G3/G4 CPUs: clarification needed
Date: Sat, 29 Apr 2006 19:57:40 +0200 (MEST) [thread overview]
Message-ID: <22904.1146333460@www017.gmx.net> (raw)
In-Reply-To: 1146174809.30710.14.camel@localhost.localdomain
> --- Ursprüngliche Nachricht ---
> Von: Benjamin Herrenschmidt <benh@kernel•crashing.org>
> An: "Mark A. Greer" <mgreer@mvista•com>
> Kopie: linuxppc-dev@ozlabs•org, debian-powerpc@lists•debian.org
> Betreff: Re: Not coherent cache DMA for G3/G4 CPUs: clarification needed
> Datum: Fri, 28 Apr 2006 07:53:29 +1000
>
> > What Ben says is correct, there is that issue. However, AFAIK, I have
> > not yet to run into it.
>
> Hrm... well, I wouldn't rely on that tho.
>
> > If that hardware workaround is not implemented, the options are:
> > a) 100% chance of a system hang with coherency on
> > or
> > b) < 0.0..1% chance of a system hang with coherency off (at least in my
> > experience to far).
> >
> > The choice is simple.
>
> I disagree. A solution that is known to have a hole in it is no good
> even if you haven't managed to trigger it so far. Now it's Gerhard's
> choice.
The choice isn't so simple (at least for me):
I read some old posts of AmigaOS4 developers in the last days. It seems they
just do cache flushes at the beginning/end and during (sync) a DMA transfer.
Also the memory used for DMA is marked as cacheable!? Only the memory used
for the PRD tables (for the IDE controller) is marked as cache inhibited.
I tried to get in contact with some OS4 developers, but I couldn't get an
answer yet. :-(
So I will try out the CONFIG_NOT_COHERENT_CACHE implementation first. As far
as I could understand OS4 does not use BATs for memory mapping, thus the
requisites are not really the same, but it's worth a try. On the other side
I don't understand why the PRD tables have to be in non cacheable memory and
I don't like the idea to modify the Linux IDE driver to do a cache
flush/invalidate for the PRD table memory area.
Thanks again for all your help!
Gerhard
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next prev parent reply other threads:[~2006-04-29 17:57 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-04-20 18:57 Not coherent cache DMA for G3/G4 CPUs: clarification needed Gerhard Pircher
2006-04-20 20:38 ` Eugene Surovegin
2006-04-20 20:56 ` Gerhard Pircher
2006-04-20 21:02 ` Eugene Surovegin
2006-04-20 21:10 ` Gerhard Pircher
2006-04-20 21:55 ` Eugene Surovegin
2006-04-20 22:08 ` Gerhard Pircher
2006-04-24 19:21 ` Mark A. Greer
2006-04-21 4:38 ` Benjamin Herrenschmidt
2006-04-21 8:03 ` Gerhard Pircher
2006-04-21 14:33 ` Brent Cook
2006-04-21 21:51 ` Benjamin Herrenschmidt
2006-04-27 21:31 ` Mark A. Greer
2006-04-27 21:53 ` Benjamin Herrenschmidt
2006-04-27 22:08 ` Mark A. Greer
2006-04-29 17:57 ` Gerhard Pircher [this message]
2006-04-20 21:06 ` Benjamin Herrenschmidt
2006-04-20 21:13 ` Eugene Surovegin
2006-04-20 21:19 ` Eugene Surovegin
2006-04-20 22:40 ` Benjamin Herrenschmidt
2006-04-20 22:39 ` Benjamin Herrenschmidt
2006-04-20 23:46 ` Gabriel Paubert
2006-04-21 0:09 ` Benjamin Herrenschmidt
2006-04-20 21:33 ` Eugene Surovegin
2006-04-20 22:41 ` Benjamin Herrenschmidt
2006-04-21 8:21 ` Gerhard Pircher
2006-04-20 21:03 ` Benjamin Herrenschmidt
2006-04-20 21:33 ` Gerhard Pircher
2006-04-20 22:07 ` Gabriel Paubert
2006-04-20 22:26 ` Gerhard Pircher
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