Subject: Re: [PATCH v3 2/5] perf/x86/intel: Record branch type

From: "Jin, Yao" <[email-masked]>
Date: Tue, 11 Apr 2017 19:51:57 +0800

On 4/11/2017 4:18 PM, Peter Zijlstra wrote:
> On Tue, Apr 11, 2017 at 09:52:19AM +0200, Peter Zijlstra wrote:
>> On Tue, Apr 11, 2017 at 06:56:30PM +0800, Jin Yao wrote:
>>> @@ -960,6 +1006,11 @@ intel_pmu_lbr_filter(struct cpu_hw_events *cpuc)
>>>   			cpuc->lbr_entries[i].from = 0;
>>>   			compress = true;
>>>   		}
>>> +
>>> +		if ((br_sel & X86_BR_TYPE_SAVE) == X86_BR_TYPE_SAVE)
>>> +			cpuc->lbr_entries[i].type = common_branch_type(type);
>>> +		else
>>> +			cpuc->lbr_entries[i].type = PERF_BR_NONE;
>>>   	}
> I was wondering WTH you did that else; because it should already be 0
> (aka, BR_NONE).

Yes. I will remove the else code. Thanks!

> Then I found intel_pmu_lbr_read_32() is already broken,
> and you just broke intel_pmu_lbr_read_64().
>
> Arguably we should add a union on the last __u64 with a name for the
> entire thing, but the below is the minimal fix.
>
> ---
> Subject: perf,x86: Avoid exposing wrong/stale data in intel_pmu_lbr_read_32()
> From: Peter Zijlstra <[email-masked]>
> Date: Tue Apr 11 10:10:28 CEST 2017
>
> When the perf_branch_entry::{in_tx,abort,cycles} fields were added,
> intel_pmu_lbr_read_32() wasn't updated to initialize them.
>
> Fixes: 135c5612c460 ("perf/x86/intel: Support Haswell/v4 LBR format")
> Signed-off-by: Peter Zijlstra (Intel) <[email-masked]>
> ---
> --- a/arch/x86/events/intel/lbr.c
> +++ b/arch/x86/events/intel/lbr.c
> @@ -507,6 +507,9 @@ static void intel_pmu_lbr_read_32(struct
>   		cpuc->lbr_entries[i].to		= msr_lastbranch.to;
>   		cpuc->lbr_entries[i].mispred	= 0;
>   		cpuc->lbr_entries[i].predicted	= 0;
> +		cpuc->lbr_entries[i].in_tx	= 0;
> +		cpuc->lbr_entries[i].abort	= 0;
> +		cpuc->lbr_entries[i].cycles	= 0;
>   		cpuc->lbr_entries[i].reserved	= 0;
>   	}
>   	cpuc->lbr_stack.nr = i;

I will add cpuc->lbr_entries[i].type = 0 in my patch.