From: "Gerhard Pircher" <gerhard_pircher@gmx•net>
To: Gabriel Paubert <paubert@iram•es>
Cc: linuxppc-dev@ozlabs•org, debian-powerpc@lists•debian.org
Subject: Re: Not coherent cache DMA for G3/G4 CPUs: clarification needed
Date: Fri, 21 Apr 2006 00:26:35 +0200 (MEST) [thread overview]
Message-ID: <25098.1145571995@www002.gmx.net> (raw)
In-Reply-To: 20060420220707.GA17593@iram.es
> --- Ursprüngliche Nachricht ---
> Von: Gabriel Paubert <paubert@iram•es>
> An: Gerhard Pircher <gerhard_pircher@gmx•net>
> Kopie: linuxppc-dev@ozlabs•org, debian-powerpc@lists•debian.org
> Betreff: Re: Not coherent cache DMA for G3/G4 CPUs: clarification needed
> Datum: Fri, 21 Apr 2006 00:07:08 +0200
>
> More details please what are the exact capabilities of the south and
> host bridges?
The southbridge is a VIA82C686B, which supports ISA DMA in the first 16MB.
The host bridge is a MAI ArticiaS. The ArticiaS has a bug in the snoop
signal logic and therefore does not support cache coherent DMA.
> I've never needed (and therefore) used floppy on my PreP boards (Motorola
> MVME2[467]xx series), but they have a south bridge (WinBond) that has 32
> bit DMA capability. This was specified in the PreP spec.
Oh, I thought PReP specifies only 24bit DMA. Okay, so the AmigaOne is more
like the i386 platform, just with a PPC cpu. ;-)
> This may also depend on the host bridge since RAM appears at 2GB on
> default PreP machines, which is an area that you can't access with
> normal ISA DMA anyway. On the MVME machines, you could map PCI addresses
> 0-16 MB anywhere in RAM by reprogramming the host bridge.
This is not the case for the AmigaOne. The RAM starts at physical address 0
(similar to CHRP). AFAIK the host bridge does not allow the remapping of the
address space. Maybe the southbridge can do this for DMA operation. I have
to investigate this. Thanks for the hint!
> > 3. How are DMA buffers used outside the kernel? Do user programs get a
> > pointer to the DMA buffer (in theory) from the device driver or is the
> > data copied to another buffer allocated by an user program?
>
> If your memory is uncacheable, you are better off copying it to
> cacheable memory. At least you are sure that you only access it
> once (trying to copy with FP registers to halve the number of
> accesses might be a big win, but you need to be careful).
Sounds like a big performance loss. I hope this is not necessary.
Thanks,
Gerhard
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prev parent reply other threads:[~2006-04-20 22:26 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-04-20 18:57 Not coherent cache DMA for G3/G4 CPUs: clarification needed Gerhard Pircher
2006-04-20 20:38 ` Eugene Surovegin
2006-04-20 20:56 ` Gerhard Pircher
2006-04-20 21:02 ` Eugene Surovegin
2006-04-20 21:10 ` Gerhard Pircher
2006-04-20 21:55 ` Eugene Surovegin
2006-04-20 22:08 ` Gerhard Pircher
2006-04-24 19:21 ` Mark A. Greer
2006-04-21 4:38 ` Benjamin Herrenschmidt
2006-04-21 8:03 ` Gerhard Pircher
2006-04-21 14:33 ` Brent Cook
2006-04-21 21:51 ` Benjamin Herrenschmidt
2006-04-27 21:31 ` Mark A. Greer
2006-04-27 21:53 ` Benjamin Herrenschmidt
2006-04-27 22:08 ` Mark A. Greer
2006-04-29 17:57 ` Gerhard Pircher
2006-04-20 21:06 ` Benjamin Herrenschmidt
2006-04-20 21:13 ` Eugene Surovegin
2006-04-20 21:19 ` Eugene Surovegin
2006-04-20 22:40 ` Benjamin Herrenschmidt
2006-04-20 22:39 ` Benjamin Herrenschmidt
2006-04-20 23:46 ` Gabriel Paubert
2006-04-21 0:09 ` Benjamin Herrenschmidt
2006-04-20 21:33 ` Eugene Surovegin
2006-04-20 22:41 ` Benjamin Herrenschmidt
2006-04-21 8:21 ` Gerhard Pircher
2006-04-20 21:03 ` Benjamin Herrenschmidt
2006-04-20 21:33 ` Gerhard Pircher
2006-04-20 22:07 ` Gabriel Paubert
2006-04-20 22:26 ` Gerhard Pircher [this message]
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