Subject: Re: 440GX MMU

From: Kumar Gala <[email-masked]>
Date: Mon, 6 Dec 2004 12:39:49 -0600

The TS provides an additional bit of address space on Book-E processors 
(440, e500, etc).  An exception automatically clears the MSR[IS, DS] 
fields which are used to compare against the TLB's TS field.

It was the case at one point in time (may still be) that on 440, the 
interrupt context was TS = 0, everything else was TS = 1.  Matt was 
going to (or may have) changed it so everything is TS = 0 so we could 
save a few TLB entries.

- kumar

On Dec 6, 2004, at 12:23 PM, Barbier, Renaud ((GE Infrastructure)) 
wrote:

>
>
> can someone explain to me the purpose of the TS bit in the 440GX TLBs?
>
> In the 440GX BSP, what is the point to map twice memory offset 0 (once 
> with TS=0 and once with TS=1).
>  Is that for context switch?
>
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