* 405GP cat /proc/interrupts
@ 2001-10-22 18:24 John F Davis
2001-10-22 18:40 ` Dan Malek
0 siblings, 1 reply; 2+ messages in thread
From: John F Davis @ 2001-10-22 18:24 UTC (permalink / raw)
To: linuxppc-embedded
Hello
I am using linux kernel 2.4.2_hhl20 (pre 2.0 CDK) with a custom modified
arch/ppc/kernel/ppc4xx_pic.c so that
it uses level, positive interrupts. Note, I have tweaked the mtdcr calls
so it modifies UIC0_PR, TR, and CR to match
our hardware. With that said, why does cat /proc/interrupts say that I am
using Edge Sensitive interrupts when I have
modified the TR register to be Level sensitive?
I am asking this, because I have a problem where I am missing interrupts
when they are generated quickly. I am hoping that
the /proc/interrupts mismatch is a clue that I have not completed the Edge
to Level interrupt modification. If you know of a file
besides ppc4xx_pic.c which needs to be modified, please let me know.
John
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* Re: 405GP cat /proc/interrupts
2001-10-22 18:24 405GP cat /proc/interrupts John F Davis
@ 2001-10-22 18:40 ` Dan Malek
0 siblings, 0 replies; 2+ messages in thread
From: Dan Malek @ 2001-10-22 18:40 UTC (permalink / raw)
To: John F Davis; +Cc: linuxppc-embedded
John F Davis wrote:
> .... With that said, why does cat /proc/interrupts say that I am
> using Edge Sensitive interrupts when I have
> modified the TR register to be Level sensitive?
Because the information printed by /proc/interrupts doesn't come directly
from the hardware registers, but rather (and irrelevant in this case) part
of the irq descriptor structure. You could set a bit in the irq descriptor
to make the print out pretty, but it won't have any effect on the system.
The proper solution is to set the the information in the irq descriptor,
and have the controller initialization read this and program the hardware
registers properly. You just skipped to the last step.
-- Dan
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
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