Subject: Re: ppc405_enet problems

From: "David Müller (ELSOFT AG)" <[email-masked]>
Date: Tue, 11 Dec 2001 08:51:33 +0100

It looks like the MII controller is not setting the error flag for the
first access (reading of PHYIR1 in find_phy(ppc405_phy.c)

Perhaps my work-around (see attached file) will help you too.

Felix Radensky wrote:

 > Hi,
 >
 > I'm trying to run the latest linuxppc_2_4_devel kernel on
 > our custom 405GP based board. I get kernel panic when an
 > attempt is made to probe for ethernet controller phy:
 >
 > Kernel panic: eth0: PHY id 0xfbc85c20 is not supported!
 >
 > The phy is National Semiconductor DP83846AVHG.
 > It works fine with Monta Vista HHL 2.0 kernel.
 >
 > What you think could be the problem ?
 >
 > TIA.
 >
 > Felix.
 >

Dave
--- 1.5/drivers/net/ppc405_phy.c	Thu Oct 25 00:44:15 2001
+++ edited/ppc405_phy.c	Mon Dec  3 16:51:05 2001
@@ -707,14 +707,17 @@
 {
 	struct fec_enet_private *fep;
 	int i;
-	uint phy_reg;
+	uint phy_reg, phy_reg2;
 	uint phytype;

 	fep = dev->priv;

 	for ( i = 0; i < MAX_NUM_PHYS; i++)
-		if (!(fec_enet_mdio_read(i, mk_mii_read(MII_REG_PHYIR1),
-						&phy_reg)))
+		if (!((fec_enet_mdio_read(i, mk_mii_read(MII_REG_PHYIR1),
+						&phy_reg)) ||
+		      (fec_enet_mdio_read(i, mk_mii_read(MII_REG_PHYIR2),
+		                                &phy_reg2))))
+
 			break;

 	fep->phy_addr = i;