From: Conn Clark <clark@esteem•com>
To: Patrick Mahoney <pmahoney@8d•com>
Cc: Cameron Rich <CameronR@nulec•com.au>,
Steven Blakeslee <BlakesleeS@embeddedplanet•com>,
linuxppc-embedded@lists•linuxppc.org
Subject: Re: mpc8xx - power save modes - PIT
Date: Thu, 17 Oct 2002 14:50:39 -0700 [thread overview]
Message-ID: <3DAF30AF.E9FF7B00@esteem.com> (raw)
In-Reply-To: 20021017195828.GA25234@segfault.usine.8d.com
Hi Everyone,
Patrick,
I can give you what I have our SCCR and PLPRCR registers set to.
However I cannot guaranty it will work for your board.
Our board's SCCR is set to 0x2260000H
This corresponse to setting
COM = 01 to set clock output to half strength
TBS = 1 to set Timebase freq source to GCLK2 divided by 16
RTDIV = 0 clock is divided by 4
RTSEL = 0 OSCM is selected
CRQEN = 1 System switches to high speed clk durring CPM activity
PRQEN = 1 System switches Normal high on interrupt
EBDF = 00 CLKOUT is GCLK2 divided by 1
DFSYNC = 0 SYNCCLK divded by 1
DFBRG = 00 BRGCLK divide by 1
DFNL = 000 divide clk by 2
DFNH = 000 divide clk by 1
RES = 0 all reserved bits set to 0
in binary
RES |COM | RES | TBS | RTDIV | RTSEL | CRQEN | PRQEN | RES | EBDF | RES | DFSYNC |
DFBRG | DFNL | DFNH | RES
0 | 01 | 000 | 1 | 0 | 0 | 1 | 1 | 00 | 00 | 00 | 00 |
00 | 000 | 000 | 00000
Our board's PLPRCR is set to 0x0090X000 in Normal High Mode
This corresponse to setting
MF = 000000001001 multiply OSCCLK by 10
SPLSS, TEXPS, and TMIST are represented by X because they are status bits
CSRC = 0 sys clk generated by DFNH
LPM = 00 Normal High Mode
CSR = 0 No reset on checkstop
LOLRE = 0 No reset on Loss Of lock
FIOPD = 0 No pulldown on address and data busss during sleep
When put into Doze Low Mode it changes to 0X00900500
CSRC = 1 sys clock generated by DFNL
LPM = 01 Doze high/low mode
Patrick Mahoney wrote:
>
> Hello people,
>
> First of all, this might help some...
>
> HW: rpxlite_dw mpc850
> SW: linux 2.4 monta vista
>
> I cut my board's consumption by 800mW by
> 1) taking off the power leds (100mA)
> 2) bypassing the power regulator (700mA)
>
> I give 2 sources of current to the board: a 5V and a 3.3V, hence
> modelising an ideal regulator. Turns out that the board regulator has
> a 66% efficiency.
>
> > > Well the 2.4 Linux kernel does not support runtime modifications to
> > > the clock rate. So what's the point of playing with CSCR?
> >
> > If the CPU is dozing The kernel will never know we changed it as long as
> > we change it back when the CPU wakes up.
>
> I 100% agree with you... But it doesn't work... Here are the results I
> get:
>
> SCCR[DFHL]:SCCR[DFNL] | Results
> (clock divisers) |
> ________________________|_______________________
>
> 2x:2x Works fine
>
> 1x:2x Never wakes up
>
> 1x:64x Kernel oopses
> output: "Caused by (from SRR1=40001000): Transfer error ack signal"
>
> SCCR[PRQEN] was '1' for all these tests.
>
> Conn: could you give me the complete values of SCCR and PLPRCR registers?
>
> Thanks again,
>
> Pat Mahoney
I hope this helps
Conn
--
*****************************************************************
If you live at home long enough, your parents will move out.
(Warning they may try to sell their house out from under you.)
*****************************************************************
Conn Clark
Engineering Stooge clark@esteem•com
Electronic Systems Technology Inc. www.esteem.com
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
next prev parent reply other threads:[~2002-10-17 21:50 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-10-16 6:00 mpc8xx - power save modes - PIT Cameron Rich
2002-10-16 13:22 ` Patrick Mahoney
2002-10-16 20:00 ` Conn Clark
2002-10-17 19:58 ` Patrick Mahoney
2002-10-17 21:50 ` Conn Clark [this message]
2002-10-16 17:29 ` Conn Clark
-- strict thread matches above, loose matches on Subject: below --
2002-10-11 13:15 Steven Blakeslee
2002-10-11 16:08 ` Patrick Mahoney
2002-10-10 18:35 Patrick Mahoney
2002-10-10 21:49 ` Conn Clark
2002-10-10 23:00 ` Patrick Mahoney
2002-10-11 1:42 ` Conn Clark
2002-10-11 15:59 ` Patrick Mahoney
2002-10-11 17:05 ` Conn Clark
2002-10-11 17:17 ` Patrick Mahoney
[not found] ` <20021021133451.GA16540@segfault.usine.8d.com>
2002-10-21 15:52 ` Conn Clark
[not found] ` <20021015225625.GA8153@segfault.usine.8d.com>
2002-10-16 1:08 ` Conn Clark
2002-10-16 15:42 ` Patrick Mahoney
[not found] ` <20021016130153.GA16430@segfault.usine.8d.com>
2002-10-16 18:14 ` Conn Clark
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