From: Michael Ellerman <patch-notifications@ellerman•id.au>
To: Nicholas Piggin <npiggin@gmail•com>, linuxppc-dev@lists•ozlabs.org
Cc: Nicholas Piggin <npiggin@gmail•com>
Subject: Re: powerpc/64s: exception optimise MSR handling
Date: Tue, 20 Sep 2016 23:07:18 +1000 (AEST) [thread overview]
Message-ID: <3sdjhk2jgmz9sC7@ozlabs.org> (raw)
In-Reply-To: <20160915090446.898-1-npiggin@gmail.com>
On Thu, 2016-15-09 at 09:04:46 UTC, Nicholas Piggin wrote:
> mtmsrd with L=1 only affects MSR_EE and MSR_RI bits, and we always
> know what state those bits are, so the kernel MSR does not need to be
> loaded when modifying them.
>
> mtmsrd is often in the critical execution path, so avoiding dependency
> on even L1 load is noticable. On a POWER8 this saves about 3 cycles
> from the syscall path, and possibly a few from other exception returns
> (not measured).
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail•com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/49d09bf2a66f4b5a6eabefb0d4
cheers
prev parent reply other threads:[~2016-09-20 13:07 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-15 9:04 [PATCH] powerpc/64s: exception optimise MSR handling Nicholas Piggin
2016-09-20 4:25 ` Michael Ellerman
2016-09-20 5:32 ` Nicholas Piggin
2016-09-20 13:07 ` Michael Ellerman [this message]
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