Subject: Re: [v2,3/7] powerpc/64s/radix: optimize TLB range flush barriers

From: Michael Ellerman <[email-masked]>
Date: Tue, 14 Nov 2017 22:12:10 +1100 (AEDT)

On Tue, 2017-11-07 at 07:53:05 UTC, Nicholas Piggin wrote:
> Short range flushes issue a sequences of tlbie(l) instructions for
> individual effective addresses. These do not all require individual
> barrier sequences, only one covering all tlbie(l) instructions.
> 
> Commit f7327e0ba3 ("powerpc/mm/radix: Remove unnecessary ptesync")
> made a similar optimization for tlbiel for PID flushing.
> 
> For tlbie, the ISA says:
> 
>     The tlbsync instruction provides an ordering function for the
>     effects of all tlbie instructions executed by the thread executing
>     the tlbsync instruction, with respect to the memory barrier
>     created by a subsequent ptesync instruction executed by the same
>     thread.
> 
> Time to munmap 30 pages of memory (after mmap, touch):
>          local   global
> vanilla  10.9us  22.3us
> patched   3.4us  14.4us
> 
> Signed-off-by: Nicholas Piggin <[email-masked]>

Applied to powerpc next, thanks.

https://git.kernel.org/powerpc/c/14001c60939a754717893672209160

cheers