From: neorf3k <neorf3k@gmail•com>
To: Anatolij Gustschin <agust@denx•de>
Cc: Linux Ppc Dev List Dev List <linuxppc-dev@lists•ozlabs.org>
Subject: Re: Problem reading and programming memory location...
Date: Tue, 26 Nov 2013 19:29:46 +0100 [thread overview]
Message-ID: <4123A441-F04D-4F4B-9DA7-B73C808D9B79@gmail.com> (raw)
In-Reply-To: <20131119224505.7a31b69c@crub>
Hi Anatolij,
we have tried again=85 but the problem is still there=85 we are not able =
to read/write, not only CS4, but also CS1, CS2, CS3, etc=85
According to you, could we fix the problem if we include our Virtex FPGA =
in Device Tree?
U-Boot has been patched (not by us), for CS4, with:
+#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS0_CFG 0x000ADD00
+#define CONFIG_SYS_CS3_START 0x10000000 //
+#define CONFIG_SYS_CS3_SIZE 0x00020000 //
+#define CONFIG_SYS_CS3_CFG 0x0002DF00 //=20
+
+#define CONFIG_SYS_CS4_START 0x10020000 //
+#define CONFIG_SYS_CS4_SIZE 0x00020000 //
+#define CONFIG_SYS_CS4_CFG 0x0002DC00 //=20
+
+#define CONFIG_SYS_CS5_START 0x11000000 //
+#define CONFIG_SYS_CS5_SIZE 0x01000000 //
+#define CONFIG_SYS_CS5_CFG 0x0002DD00 //=20
+
+#define CONFIG_SYS_CS_BURST 0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
+
+#define CONFIG_SYS_RESET_ADDRESS 0xff000000
but CONFIG_SYS_CS4_SIZE should be: 0x00010000 ...
Thank you
Lorenzo
On 19/nov/2013, at 10:45 PM, Anatolij Gustschin <agust@denx•de> wrote:
> Hi Lorenzo,
>=20
> On Tue, 19 Nov 2013 11:20:24 +0100
> neorf3k <neorf3k@gmail•com> wrote:
>=20
>> Hello Anatolij, this is our code, used at University, but again it =
doesn=92t work=85
>>=20
>> How i told, the only information we have about that reg are:
>>=20
>> Chip select 4 specification:
>> Lp_cs4
>> bus size: 8 bit
>> bus control: 2 wait state R/W ACK disabled
>> size allocated: 4 KByte
>>=20
>> Our Register 8 bit LP_cs4 (we want to write)
>>=20
>> cs4 offset: 0x001
>=20
> is the byte in FPGA at offset 0x0 writable? In your code you
> currently test read/write access to the byte at offset 0x0.
>=20
> If the read/write access works under U-Boot, then maybe the
> chip select parameters for CS4 are configured differently
> in U-Boot. You can dump the Chip Select 4 configuration
> registers under U-Boot and compare. Is address- and data-bus
> to the FPGA multipexed? Another possible reason for non-working
> access could be that the configured CS4 range 0x10020000 - 0x10030000
> overlaps with configured range for CS0, CS1, CS2 or CS3. Can you
> verify that no such overlapping exists.
>=20
> Thanks,
>=20
> Anatolij
prev parent reply other threads:[~2013-11-26 18:29 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-12 19:23 Problem reading and programming memory location neorf3k
2013-11-13 7:32 ` Anatolij Gustschin
2013-11-13 13:48 ` neorf3k
2013-11-13 18:06 ` Anatolij Gustschin
2013-11-14 8:38 ` neorf3k
[not found] ` <20131114100917.31f674d7@crub>
2013-11-14 9:49 ` neorf3k
2013-11-15 16:27 ` neorf3k
2013-11-16 14:29 ` Anatolij Gustschin
2013-11-16 15:11 ` neorf3k
2013-11-19 10:20 ` neorf3k
2013-11-19 21:45 ` Anatolij Gustschin
2013-11-26 18:29 ` neorf3k [this message]
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