From: Clemens Koller <clemens.koller@anagramm•de>
To: Dan Malek <dan@embeddededge•com>
Cc: linuxppc-embedded@ozlabs•org
Subject: Re: MPC85xx DMA support for Kernel 2.6?
Date: Mon, 04 Jul 2005 11:03:33 +0200 [thread overview]
Message-ID: <42C8FB65.1030309@anagramm.de> (raw)
In-Reply-To: <d67d2bddad7bf2be742b8d53768482bf@embeddededge.com>
Hi, Dan and Mark!
Dan Malek wrote:
> On Jul 1, 2005, at 10:15 AM, Mark Chambers wrote:
>
>> Is the SRAM being cached? I don't think the CPU will generate bursts
>> unless it's cached, right?
>
> I don't really remember :-) I know the 8xx will not burst if the line
> isn't
> cached, and I know the 7xxx will. I thought the 82xx and 85xx would
> also burst if you had sufficient sequential operations queued. On
> 83/85xx you have to further qualify the discussion based upon the DDR2
> or the local bus interface :-) The CPM and DMA will burst on all
> buses for 8xx/82xx/83xx/85xx if the memory controller is configured
> to do so.
Thanks, for your comments! I'll have a look at it during the
next days and let you know about my mileage :-)
Greets,
Clemens Koller
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prev parent reply other threads:[~2005-07-04 9:03 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-06-30 15:12 MPC85xx DMA support for Kernel 2.6? Clemens Koller
2005-06-30 15:30 ` Kumar Gala
2005-06-30 15:56 ` Clemens Koller
2005-06-30 16:57 ` Murray.Jensen
2005-07-01 7:54 ` Clemens Koller
2005-07-01 8:36 ` Murray.Jensen
2005-07-01 13:59 ` Kumar Gala
2005-06-30 18:52 ` Dan Malek
2005-07-01 7:47 ` Clemens Koller
2005-07-01 14:02 ` Dan Malek
2005-07-01 14:15 ` Mark Chambers
2005-07-01 21:49 ` Dan Malek
2005-07-04 9:03 ` Clemens Koller [this message]
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