Subject: Re: [PATCH] powerpc: Merge align.c

From: Andrey Volkov <[email-masked]>
Date: Wed, 16 Nov 2005 19:54:31 +0300

Becky Bruce wrote:
> On Nov 15, 2005, at 8:34 PM, Benjamin Herrenschmidt wrote:
> 
>> >
>> > BTW, Based on the pile of docs I have here, I think the list of
>> > alignment-exception-causing events on FSL's current parts (603, 603e,
>> > 750, 74x, 74xx, e500) is:
>> >
>> > - lmw/stmw (all procs, non-word aligned)
>> > - single and double precision floating point ld/st ops (non-E500, non
>> > data size aligned)
>> > - dcbz to WT or CI memory (all procs)
>> > - dcbz with cache disabled (all procs but 603e?)
>> > - misaligned little endian accesses (603e)
>> > - lwarx/stwcx (all procs)
>> > - multiple/string with LE set (750, 603e, 7450, 7400)
>> > - eciwx/ecowx (750, 7450, 7400)
>> > - a couple of others related to vector processing
>> >
>> > If anybody knows offhand of something missing there, let me know.
>>
>> What about lwz/stw cropssing page boundaries ? Is this handled in HW ?
>>
>> Ben.
> 
> 
> Apparently so, much to my surprise - I ran the testcase with those
> instructions misaligned across a page boundary last night and got no
> alignment exception.  I was surprised, and asked my husband about it (he
> worked on the load/store units for a bunch of our parts), and he says
> these guys never cause an exception for any of FSL's current parts as
> far as he knows.  This is supported by our documentation as well - the
> only place I see these listed is on 603e, where they can cause an
> exception if the page is mapped little endian.
> 
Try this for 603e (BE):
 memcpy(xxxx3, xxxx0, 8);

I get invalid behavior (0 in second dword) on MPC5200 for external flash
access.

--
Regards
Andrey Volkov