Subject: Yosemite/440EP 'issues' as a PCI target

From: David Hawkins <[email-masked]>
Date: Thu, 09 Feb 2006 15:58:13 -0800

Hi all,

I'm evaluating the 440EP for use as the control processor
on a PCI peripheral. Today I have been looking at what I
can use for processor-to-processor communications over
the PCI bus. The boards will be used in existing
equipment that does not have ethernet in the backplane.

It appears that the 440EP has very limited options for
interrupt-based communications over the PCI bus.

Lets assume the following basic host-to-host protocol
(interrupt-based handshake).

1) PCI system slot machine 'host' has all the IRQs routed
    to it. This will be an x86-based machine.
    The host interrupts the device when it wants to
    send it data, or when it wants to send an acknowledge.

2) PCI device slot; a 440EP based board.
    The device interrupts the host when it wants
    to send it data, or when it wants to send an
    acknowledge.

If the 440EP board wants to interrupt the host, it can
generate an interrupt by writing to the PCI Interrupt
Control/Status Register, PCIC0_ICS, with only 1 bit
available for interrupt generation (i.e., there is
no concept of a mailbox or doorbell register, just a bit)
(see p388 of the v1.18 manual).

Now what if the host wants to interrupt the 440EP.
Errr, there is no register defined for this purpose.
The UIC chapter, p220-222 v1.18 manual indicates
all the interrupt bits. Sure there are a couple of
PCI source interrupts, one for writes to the PCI
configuration-space command register (so can't really
use that), and another for power-management events.

Have I missed something?

I'll have an FPGA/CPLD on the external bus, so I guess
I can implement a mailbox/doorbell register in that
and then have that register trigger an external interrupt
on the 440EP. The 440EP PCI target BARs will then need
to be setup to decode to the EBC decode range.
Sounds like a hack ... (even more of a hack is to
loop back a GPIO onto an EXTINT and setup the target
decode to cover the GPIO registers, and the x86 can
toggle a GPIO directly).

Of course if I have a few unused peripherals I might
be able to cause them to generate an interrupt. But
that gets tricky since in a lot of cases, as device
interrupts are often controlled via DCRs.

I realize that some of the other devices have I2O messaging
units (440GX and 440SP), so are more suited to PCI comms
applications. However, I require the hardware FPU on
the 440EP. From the selector guide, its only the 440EP
and 440EPx that contain the FPU.

Any comments on this?
Dave