Wade,

the v4fx60 has two PPC405. Please make sure that both PPC405 are 
connected to the jtagppc_cntrl in your MHS hardware project file. You 
might want to compare your setup with the ML410 reference design 
available at 
http://www.xilinx.com/products/boards/ml410/designs/ml410_bsb_design.zip.

The JTAG IR length of the v4fx60 is 14 (6 for the FPGA + 4 for each 
PPC405, i.e. for the 4vfx60 it's 6+4+4=14)

- Peter


Wade Maxfield wrote:

> Hi,
>
>   We are trying to generate a system ace file that will program an 
> xf60 using Xilinx scripts,
> (and even their impact GUI), using 8.1i, service pack 3 EDK.
>
>   Unfortunately, if we choose the ml410 board from Xilinx's genace.tcl 
> script
> in their EDK/data/xmd directory, it errors with an invalid instruction 
> register length.
> The irlength is listed as 14 in the xilinx script files.  I looked and 
> googled and could
> not find the irlength listed for that xf60 part in any literature.
>
>   Also, if we try to include the zImage.elf file, the script errors out.
>
>   Conversely, if we choose an ml403 board (and switch the project to 
> the xf12 chip),
> we can combine the zImage.elf file and generate a system.ace file that 
> loads on an
> ml403 board.
>
>   We can take the download.bit file that refuses to load when combined 
> into the system.ace,
> and load it over the jtag port.  It programs the xf60 just fine.
>
>   If we create an empty system.ace file,  the system ace chip on our 
> board signals everything is ok,
> but of course, the xilinx chip is not programmed.  If we pull the 
> compact flash out of the board,
> the system ace chip signals that is can't find the compact flash by 
> flashing the error light.
>
>   Has anyone on this list had any experience with this that could lead 
> us in a right direction?  We've
> tried about 10 different combinations so far with no luck.
>
> thanks,
> wade
>
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