Subject: Re: Mr Grant Likely's New Patches for 2.6 Kernel and Xilinx FPGA ( Virtex-4 & Virtex-2

From: Andrei Konovalov <[email-masked]>
Date: Mon, 16 Apr 2007 20:51:57 +0400

Grant Likely wrote:
> On 4/16/07, Andrei Konovalov <[email-masked]> wrote:
>> Grant Likely wrote:
>> > No, I did not include TEMAC support.  However, I will publish my git
>> > tree tomorrow which will include the TEMAC driver.
>>
>>
>> Seems the TEMAC driver is not on your git server yet. Hence the 
>> questions.
>> Guess this is PLB TEMAC version 3.00a as you wrote auto negotiation is 
>> supported.
> 
> yup
> 
>> Is your driver based on the one by Xilinx (the one from EDK 8.2.02 and 
>> the update posted by Rick Moleres)?
> 
> Yup, it's just the adapter.c file that Rick posted plus some fixups to
> get it to compile in my tree.  Nothing really exciting.  I'm very
> interested in the phylib work that you've done.  I hope to take a look
> at that in the next day or so.

The feedback is very welcome.
Mostly was trying to use what is already in the kernel, and not to reinvent
the wheel.

I wouldn't say I've completely done with it.
Few SGDMA related ioctls to add (should be fairly straightforward).
And to check the advertised capabilities - as I wrote in the previous
posting, it looks like the driver stops advertising 1000Mbits at some
point (after turning auto negotiation off, switching to the lower speeds,
and trying to go back to 1000Mbits).

> I'm only publishing my tree as a
> convienient starting point for those who need it.
> 
> Ideally, I'd like to look at doing a full rewrite so it's in a
> condition acceptable for mainline, but I don't have time for that at
> the moment.

I am not certain if the "linux adapter plus the OS independent code"
could easily be accepted (provided that the OS independent code is
reformatted as much as possible to fit into the community).
Afraid complete rewrite is fairly large effort, and, moreover, so far PLB TEMAC
has been significantly changing from one EDK release to the next. So
one could have to rewrite considerable parts of the driver every EDK release.
Would be nice to reuse the man-hours Xilinx put in their OS indpendent code.

Thanks,
Andrei

> Cheers,
> g.