Subject: Re: powerpc_flash_init(), wtf!?

From: Sergei Shtylyov <[email-masked]>
Date: Thu, 03 May 2007 21:17:53 +0400

Hello.

Segher Boessenkool wrote:

>>>>   We weren't aware of the of_platform.c work when writing the MTD 
>>>> support.
>>>>   Note that this function usually probes only the specified set of 
>>>> (SoC)
>>>> busses, none of which usully contains NOR flash (which is located at 
>>>> the
>>>> root level).

>>> The root level?  Um... I don't think so...

>>     "Trust me". :-)
>>     NOR flashes are at the same level as the "memory" node (where else 
>> you
>> expect them to appear I wonder?).

> The "memory" node doesn't describe the RAM devices;
> it describes the RAM address space, instead.  You can
> have separate nodes for the actual devices.

    If you can remember our prior discussion, the "rom" nodes don't describe 
"the actual devices" as well, only their mapping into the address space. ;-)

> Now for ROM/flash/NVRAM, nodes _can_ appear directly
> under the root, but only if that is where they belong
> on your platform (i.e., they sit directly on the "system
> bus" (whatever that means on your platform); on most
> platforms though, such devices are connected via some
> I/O busses, so the nodes should appear under their
> respective controllers.

    Yeah, you're right here, and I've probably misunderstood what "memory" 
node was. In fact, the flash in my system resides on the same local bus as 
RAM, so the proper place would be behind the "lbc" (or whatever -- it doesn't 
exist as yet) node on the "soc" bus.  Do you think I need to go and document 
it as well for such cause? :-]

>>> I believe the arrangement is similar for most other 4xx systems.  More
>>> PC or desktop like systems sometimes have boot flash connected to the
>>> south bridge, which I believe puts it on the ISA bus, topologically
>>> speaking.

> Some have it on the LPC bus as an LPC device, some
> have it on the LPC bus but accessed with a separate
> protocol,  some have it attached to another LPC device
> (some "superio" typically), some have it attached
> directly to the "south bridge".

>>     Not exactly. Boot flash is mapped beyond ISA address space on 386+ 
>> -- at
>> the top of 4GB (where the "reset vector" is). Although it may be dual 
>> mapped
>> below 1MB as well (I'm starting to forget x86 :-).

> Most "north bridges" have some bits that enable
> translation of accesses in the "low bios" area to
> the 4GB-minus-a-bit area.  There are many variations
> and it all is a big mess :-)

    Human perversion knows no limits. O:-)

> Now, back to the case at hand -- it would be nice to
> have a platform-independent way to probe the simple
> case -- a single direct-mapped device -- but it isn't
> obvious how to make that not clash with the not-so-simple
> cases.  A helper function that does the work but is
> only called by the platforms that want it would do, I
> suppose?

    It probably doesn't even worth a helper (since out of those 15 lines, 6 
were pretty useless anyway)

> Segher

WBR, Sergei